> For the complete documentation index, see [llms.txt](https://docs.hackerfab.org/home/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://docs.hackerfab.org/home/metrology-and-characterization/electrical-characterization/c-v-characterization/mos-c-v-characterization.md).

# MOS C-V Characterization

C-V characterization is one of the most useful techniques for studying **MOS (metal-oxide-semiconductor) structures.** By changing the voltage applied to the gate, we change the distribution of charge near the semiconductor-oxide interface. This produces the characteristic accumulation, depletion, and inversion regions of the C-V curve.

A basic MOS capacitor consists of a conductive gate separated from the semiconductor by a thin dielectric layer:

<figure><img src="https://2353182699-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FXgXjz6D0Vz2o0EOp8JO5%2Fuploads%2FiclpKNHT9IrinHL8bGPM%2FMOS%20Cap.png?alt=media&amp;token=dbe26e3c-4c4d-4dd5-a959-bc2f8b39949a" alt="" width="375"><figcaption><p><strong>Schematic cross-section of a MOS capacitor</strong></p></figcaption></figure>

For an ideal MOS capacitor, the oxide capacitance is:

$$
C\_{ox} = \frac{\epsilon\_{ox}A}{t\_{ox}}
$$

where $$A$$ is the gate area, $$t\_{ox}$$ is the oxide thickness, and $$\epsilon\_{ox}$$ is the permittivity of the oxide.

### Accumulation, depletion and inversion

<figure><img src="https://2353182699-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FXgXjz6D0Vz2o0EOp8JO5%2Fuploads%2FSy7ZZFdqyqEmCHfROQem%2FProcess.png?alt=media&amp;token=3a1ad0b3-5df4-4fb3-a4a2-ed53ea617f58" alt="" width="563"><figcaption><p><strong>Charge distribution in a MOS capacitor with a p-type substrate</strong></p></figcaption></figure>

Consider a MOS capacitor fabricated on a **p-type substrate.** As the gate voltage is changed, the charge distribution near the semiconductor surface changes.

#### Accumulation

When a negative voltage is applied to the gate, holes are attracted toward the semiconductor-oxide interface. The majority carriers accumulate close to the surface. In this region, the measured capacitance approaches the oxide capacitance:&#x20;

$$
C \approx C\_{ox}
$$

#### Depletion

As the gate voltage becomes more positive, holes are repelled from the semiconductor surface. This creates a **depletion region** containing ionized acceptor atoms but few mobile carriers.\
\
The depletion region behaves like an additional capacitance:

$$
C\_{dep} = \frac{\epsilon\_s A}{W\_d}
$$

where $$W\_d$$ is the depletion width.\
\
The oxide and depletion capacitances effectively appear in series:

$$
\frac{1}{C} = \frac{1}{C\_{ox}} + \frac{1}{C\_{dep}}
$$

As the depletion region becomes wider, $$C\_{dep}$$ decreases, causing the measured capacitance to decrease.

#### Inversion

With sufficiently positive gate voltage, the surface concentration of electrons becomes large enough to form an **inversion layer** near the semiconductor-oxide interface.

What happens to the measured capacitance in this region depends strongly on the feequency of the measurement signal.

### Low and high frequency C-V

The behavior of MOS capacitor in inversion depends strongly on the frequency of the AC measurement signal.

<figure><img src="https://2353182699-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FXgXjz6D0Vz2o0EOp8JO5%2Fuploads%2FtyvUqoDWwek0wXibkm28%2FCV%20graph.png?alt=media&amp;token=3d5705b4-a71e-4154-b3a9-359d34faf851" alt="" width="563"><figcaption><p><strong>Schematic low- and high-frequency C-V characteristics of a MOS capacitor with a p-type substrate</strong></p></figcaption></figure>

At **low frequencies**, minority carries have enough time to respond to the changing AC signal. In a p-type substrate, electrons can move toward and away from the semiconductor surface as the AC voltage changes. As a result, the inversion layer contributes to the small-signal response and the measured capacitance increases again toward $$C\_{ox}$$.

At **high frequencies**, minority carriers cannot respond quickly enough to the AC signal. The inversion charge therefore remains approximately constant during each AC cycle. Changes in the AC voltage mainly change the width of the depletion region.\
\
Once the depletion region reaches approximately its maximum width, the measured capacitance approaches a minimum value, $$C\_{min}$$.\
\
The minimum capacitance is determined by the series combination of the oxide capacitance and the maximum depletion capacitance:

$$
\frac{1}{C\_{min}} = \frac{1}{C\_{ox}} + \frac{1}{C\_{dep\_{max}}}
$$

where:

$$
C\_{dep\_{max}} = \frac{\epsilon\_s A}{W\_{d\_{maxs}}}
$$

### Parameter Extraction

A measured MOS C-V curve can be used to extract several physical and electrical parameters of the device.

#### Oxide Capacitance and Thickness

The oxide capacitance $$C\_{ox}$$ can be estimated from the accumulation region, where the measured capacitance approaches the oxide capacitance.\
\
Once $$C\_{ox}$$ is known, the oxide thickness can be estimated from:

$$
t\_{ox} =
\frac{\epsilon\_{ox}A}{C\_{ox}}
$$

For silicon dioxide:

$$
\epsilon\_{ox} = \epsilon\_0 \epsilon\_r
$$

with $$\epsilon\_r \approx 3.9$$.\
\
This make C-V measurement a useful method for estimating the thickness of thin gate dielectrics.

#### Flat-Band Voltage

The **flat-band voltage** $$V\_{FB}$$ is the gate voltage at which there is no band bending in the semiconductor.\
\
For an ideal MOS structure, it is determined by the work-function difference between the gate and semiconductor. In a real device, oxide and interface charges can shift the flat-band voltage:

$$
V\_{FB} = \phi\_{ms} - \frac{Q\_{ox}}{C\_{ox}}
$$

where $$\phi\_{ms}$$ is the gate-semiconductor work-function difference and $$Q\_{ox}$$ represents the effective oxide charge.

The position of the measured C-V curve relative to the ideal characteristic can therefore provide information about charge present in the oxide or near the semiconductor-oxide interface.

#### Threshold Voltage

The **threshold voltage** $$V\_{TH}$$ marks the transition into strong inversion.\
\
For a p-type substrate, the ideal MOS threshold voltage can be written approximately as:

$$
V\_{TH} = V\_{FB} + 2\phi\_F +
\frac{\sqrt{4q\epsilon\_s N\_A\phi\_F}}{C\_{ox}/A}
$$

where $$N\_A$$ is the acceptor concentration and $$\phi\_F$$ is the Fermi potential, $$q$$ is the elementary charge, and $$\epsilon\_s$$ is the semiconductor permittivity.

In practice, threshold voltage can be estimated from the measured C-V characteristic using the extracted device parameters.

#### Substrate Doping

The depletion region of the MOS capacitor depends on the doping concentration of the semiconductor. Because this depletion region contributes to the measured capacitance, the C-V curve can be used to estimate the substrate doping.

The depletion capacitance per unit area is:

$$
C\_{dep} = \frac{\epsilon\_s}{W\_d}
$$

and the depletion width depends on the semiconductor doping concentration. This means that the shape of the C-V curve in depletion contains information about the doping of the substrate.

#### Interface Traps

Defects at the semiconductor-oxide interface can create electronic states known as **interface traps**.

These traps can exchange charge with the semiconductor and affect the measured C-V characteristic. Depending on their response time and the measurement frequency, they can stretch or distort the C-V curve and introduce frequency-dependent behaviour.

The density of interface traps, usually written as $$D\_{it}$$, can be estimated using several C-V measurement techniques, including comparisons between measurements performed at different frequencies.

#### Non-ideal C-V Characteristics

Real MOS capacitors rarely produce an ideal C-V characteristic. Difference between the measured and ideal curves can provide useful information about the quality of the oxide and semiconductor-oxide interface.\
\
Common non-ideal effects include:

* **oxide charge**, which can shift the C-V curve along the voltage axis,
* **interface traps**, which can stretch or distort the transition between regions,
* **hysteresis**, where the measured curve depends on the direction of the voltage sweep,
* **frequency dispersion**, where the measured capacitance changes with measurement frequency,
* **leakage current**, which can affect the accuracy&#x20;
* **series resistance**, which can introduce measurement errors, particularly at higher frequencies.

Because of these effects, measurements at different frequencies and sweep directions can provide additional information about the MOS structure.

### References

* Robert F. Pierret, Semiconductor Device Fundamentals, Addison-Wesley, 1996, Chapter 16: “MOS Fundamentals,” Section 16.4: “Capacitance-Voltage Characteristics.”


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