> For the complete documentation index, see [llms.txt](https://docs.hackerfab.org/home/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://docs.hackerfab.org/home/processes/cmos-sputtered-gate-stack-wip.md). # CMOS - sputtered gate stack (WIP) ## Overview Contact - Jay Kunselman This is in support of the development of a CMOS process that uses a Si-Al2O3-Al gate stack. The NMOS process originally developed with Hacker Fab tooling relies on procuring wafers that already have a Si-SiO2-PolySi prefabricated gate. This prevents the expansion of the NMOS process into a CMOS process. For a CMOS process, it is necessary for the gate stack to be fabricated in house with Hacker Fab tooling. Sputtering of the gate stack from just an Al target is pursued as a potential option to mitigate the risks associated with gate oxide contamination. For context, growing a SiO2 gate oxide has been considered, but abandoned due to a few challenges. The main being contamination control of the gate oxide in an open air tube furnace, contamination that can be introduced between oxide growth and metal deposition for the gate, and the added complexity of dopant pile up + depletion (discussed in the Oxidation Effects Section of "Microchip Fabrication: A Practical Guide to Semiconductor Processing by Peter Van Zant"). Overall this intended process simplifies the tooling required to tape out devices (cuts out evaporator and plasma etcher). Sputtering allows for a low contamination oxide to be deposited, which is immediately covered with a metal gate contact without the chip ever exiting the clean vacuum environment of the sputtering chamber. The choice of Al2O3 as the oxide and Al as the metal is motivated by simplified process flow it allows, and relatively inexpensive target material (Al2O3 is sputtered reactively form an Al target, then Al is sputtered immediately after from the same target, avoiding the need for a 2 target system or a target swapping). Al2O3 has favorable dielectric constant and band alignment, but there are risks related to charge traps forming at the Si-Al2O3 interface. Attempts are made to tune the process to mitigate this interface effect. **Thus far only NMOS devices have been fabbed to verify effectiveness of sputtered gate oxide. Details on n well doping process dev to allow for CMO devices coming soon** **More details on general approach and methods and next steps coming soon** The sputtered film characterization that precedes this work is linked below. {% content-ref url="/pages/kwEeY6PeKfSmJPhem9fF" %} [Film Characterization](/home/fab-toolkit/deposition/diy-rf-sputtering-chamber/film-characterization.md) {% endcontent-ref %} ## MOSCap Capacitance and Conductance Profiling MOSCap devices were fabricated from the sputtered Al and Al2O3 for Conductave-Voltage and Capacititacne voltage profiling. They were fabricated from the process flow inlcuded below from prime p-Si 5-10 ohm (100) wafers. Oxide thickness, surafce preparation method, and post oxide deposition anealing were modulated to study the impact on capcitance and conductance testing.The individual MOSCaps were defined by applying a shadowmask in between the oxide deposition and the first Al deposition.![](https://images.gitbook.com/__img/dpr=2,width=760,onerror=redirect,format=auto,signature=1516433323/https%3A%2F%2Ffiles.gitbook.com%2Fv0%2Fb%2Fgitbook-x-prod.appspot.com%2Fo%2Fspaces%252FXgXjz6D0Vz2o0EOp8JO5%252Fuploads%252FQNcqMQmTzeiPyuuUPqBi%252Fimage.png%3Falt%3Dmedia%26token%3D88094732-bee1-4537-8c91-6c32dcba0c3c)

Step #	Step Name	Parameters
0	Substrate Stack	Si p-type 5-10 ohms (100): 525 µm
1	RCA Clean	SC 1 Constituents: H2O:NH4OH(29%):H2O2(30%) (5:1:1) SC 1 Cleaning Time: 10 mins SC 1 Cleaning Temperature: 80 °C HF Concentration: 6:1 BOE HF Dip Time: 15 secs HF Dip Temperature: 20 °C SC 2 Constituents: H2O:HCl(37%):H2O2(30%) (6:1:1) SC 2 Cleaning Time: 10 mins SC 2 Cleaning Temperature: 80 °C "SC 1 and 2 mixed in 50ml pyrex beakers directly before using. Optional HF last processing step (Experimental Option) Rinsed with DI Water then N2 dried. Immediately placed into sputtering chamber for pump down."
2	Sputter w/ CMU Hacker Fab RF Sputtering Chamber	Material: Al2O3 Film thickness: Experimental Option Deposition Rate: .00025 µm/min Deposition Time: 80 mins Sputter Type: RF Sputtering RF or DC Power: 100 Watts Sputter Gas Composition: 9 SCCM UHP Ar : 9 SCCM UHP O2 Chamber Pressure: 4.7E-3 Torr Throw Distance: 3" Base Pressure Pre Deposition: 1E-7 Torr Target Sputter Clean Ar Flow: 30 SCCM Target Sputter Clean Time: 15 Minutes
3	Anneal (Experimental Option)	Performed in RF sputtering Chamber under partial Vacuum. Pump speed at 250Hz with 50 SCCM of either UHP Ar or UHP O2.
4	Sputter w/ CMU Hacker Fab RF Sputtering Chamber	Material: Al Film thickness: 150 nm Deposition Rate: .0025 µm/min Deposition Time: 60 mins Sputter Type: RF Sputtering RF or DC Power: 100 Watts Sputter Gas Composition: 15 SCCM UHP Ar Chamber Pressure: 3E-3 Torr Throw Distance: 3" Base Pressure Pre Deposition: 1E-7 Torr Target Sputter Clean Ar Flow: 30 SCCM Target Sputter Clean Time: 15 Minutes SWR During Deposition: 1.5
6	Sputter w/ CMU Hacker Fab RF Sputtering Chamber	Material: Al Film thickness: 150 nm Deposition Rate: .0025 µm/min Deposition Time: 60 mins Sputter Type: RF Sputtering RF or DC Power: 100 Watts Sputter Gas Composition: 15 SCCM UHP Ar Chamber Pressure: 3E-3 Torr Throw Distance: 3" Base Pressure Pre Deposition: 1E-7 Torr Target Sputter Clean Ar Flow: 30 SCCM Target Sputter Clean Time: 15 Minutes SWR During Deposition: 1.5

Summary/Comparison

| Processing Conditions | Al2O3 thickness (nm) | K (raw data) | K (slope method, raw data) | Vfb (P -> N, raw data) | Vfb (N -> P, raw data) | delta Vfb (raw data) | k (corrected data) | k (slope method, corrected data) | Vfb (P -> N, corrected data) | Vfb (N -> P, corrected data) | delta Vfb (corrected data) | G peak (Siemens) (P -> N) | G peak (Siemens) (N -> P) | Series Resistance (Ohms) (calculated) | | --------------------------------- | -------------------- | ------------ | -------------------------- | ---------------------- | ---------------------- | -------------------- | ------------------ | -------------------------------- | ---------------------------- | ---------------------------- | -------------------------- | ------------------------- | ------------------------- | ------------------------------------- | | Standard RCA clean | 45 | 7.1 | 4.7 | -0.20 | -1.15 | 0.95 | 7.2 | 4.9 | -0.20 | -1.10 | 0.90 | 2.2E-05 | 2.3E-05 | 565.95 | | Standard RCA clean | 15 | 5.3 | 2.4 | -0.80 | -1.20 | 0.40 | 5.5 | 2.5 | -0.70 | -1.00 | 0.30 | 8.3E-05 | 8.3E-05 | 495.45 | | HF-Last RCA clean | 45 | 7.4 | 4.7 | -1.90 | -2.20 | 0.30 | 7.4 | 4.8 | -1.85 | -2.15 | 0.30 | 1.9E-05 | 2.0E-05 | 260.67 | | HF-Last RCA clean | 20 | 6.6 | 3.2 | -1.05 | -1.85 | 0.80 | 6.7 | 3.4 | -0.95 | -1.70 | 0.75 | 7.5E-05 | 8.3E-05 | 289.87 | | HF-Last RCA clean, 450C O2 anneal | 20 | 4.7 | 2.8 | -4.35 | -4.70 | 0.35 | 5.3 | 3.1 | -4.15 | -4.45 | 0.30 | 8.1E-05 | 9.0E-05 | 910.06 | ## MOSCap Leakage Current

## MOSFETs and TLM Test Structures

#### General MOSFET Process Multiple steps modified for experimentatal conditions noted below

Step #	Step Name	Parameters
0	Substrate Stack	p-Si 5-10 ohm (100): 525 µm
1	Acetone + IPA Clean (N2 dry)	Cleaning Agent: Acetone then IPA Squirt with Acetone, then IPA, then dry the surface with the N2 gun.
2	Bake	Bake Temperature: 100 °C Bake Time: 60 secs
3	Spin-Coat	Material Type: Adhesion Promoter Material: HMDS Spin Speed: 4000 rpm Spin Time: 30 secs
4	Bake	Bake Temperature: 100 °C Bake Time: 60 secs
5	Spin Resist	Resist: AZ P4210 Resist Type: Positive Spin Speed: 4000 rpm Spin Time: 30 secs
6	Bake	Bake Temperature: 100 °C Bake Time: 90 secs
7	Hacker Fab Maskless Litho Stepper	Exposure time: 8 secs
8	Develop	Developer: AZ 400K : DI Water (1:3) Develop Time: 30 secs
9	Wet-Etch	Actually performed with SF6 RIE, but can be replaced by a Nitric + HF wet etch solution since this step simply creates alignment marks in the Si.
10	Wet Strip Resist	Stripping Agent(s): Acetone then IPA Blow dry with N2 gun after.
11	RCA Clean	SC 1 Constituents: H2O:NH4OH(29%):H2O2(30%) (5:1:1) SC 1 Cleaning Time: 10 mins SC 1 Cleaning Temperature: 80 °C HF Concentration: 6:1 BOE HF Dip Time: 15 secs HF Dip Temperature: 20 °C SC 2 Constituents: H2O:HCl(37%):H2O2(30%) (6:1:1) SC 2 Cleaning Time: 10 mins SC 2 Cleaning Temperature: 80 °C
12	Spin-Coat	Material Type: Non-Resist Material: 700B (spin on glass) Spin Speed: 4000 rpm Spin Time: 20 secs
13	Bake	Bake Temperature: 400 °C Bake Time: 10 mins
14	Spin-Coat	Material Type: Adhesion Promoter Material: HMDS Spin Speed: 4000 rpm Spin Time: 30 secs
15	Bake	Bake Temperature: 100 °C Bake Time: 60 secs
16	Spin Resist	Resist: AZ P4210 Resist Type: Positive Spin Speed: 4000 rpm Spin Time: 30 secs
17	Bake	Bake Temperature: 100 °C Bake Time: 90 secs
18	Hacker Fab Maskless Litho Stepper	Exposure time: 8 secs
19	Develop	Developer: AZ 400K : DI Water (1:3) Develop Time: 30 secs
20	Wet-Etch	Etch Time: 20 secs Etching Agent(s): 6:1 BOE
21	Wet Strip Resist	Stripping Agent(s): Acetone then IPA Blow dry with N2 gun after.
22	Spin-On Dopant	Spin-On Dopant Name: P504 (Phosphorus source) Spin Speed: 4000 rpm Spin Time: 20 secs
23	Bake	Bake Temperature: 200 °C Bake Time: 10 mins
24	Dopant Diffusion	Diffusion Time: 30 mins Diffusion Temperature: 1100 °C Environmental: false
25	Wet-Etch	Etch Time: 10 mins Etching Agent(s): 6:1 BOE
26	RCA Clean	SC 1 Constituents: H2O:NH4OH(29%):H2O2(30%) (5:1:1) SC 1 Cleaning Time: 10 mins SC 1 Cleaning Temperature: 80 °C HF Concentration: 6:1 BOE HF Dip Time: 15 secs HF Dip Temperature: 20 °C SC 2 Constituents: H2O:HCl(37%):H2O2(30%) (6:1:1) SC 2 Cleaning Time: 80 mins SC 2 Cleaning Temperature: 75 °C
27	Sputter w/ CMU Hacker Fab RF Sputtering Chamber	Material: Al2O3 Film thickness: 20 nm Deposition Rate: .25 Å/s Deposition Time: 80 mins Sputter Type: RF Sputtering RF or DC Power: 100 Watts Sputter Gas Composition: 9 SCCM UHP Ar : 9 SCCM UHP O2 Chamber Pressure: 4.7E-3 Torr Throw Distance: 3" Base Pressure Pre Deposition: 1E-7 Torr Target Sputter Clean Ar Flow: 30 SCCM Target Sputter Clean Time: 15 Minutes SWR During Deposition: 1.5
28	Sputter w/ CMU Hacker Fab RF Sputtering Chamber	Material: Al Film thickness: 150 nm Deposition Rate: 2.5 Å/s Deposition Time: 60 mins Sputter Type: RF Sputtering RF or DC Power: 100 Watts Sputter Gas Composition: 15 SCCM UHP Ar Chamber Pressure: 3E-3 Torr Throw Distance: 3" Base Pressure Pre Deposition: 1E-7 Torr Target Sputter Clean Ar Flow: 30 SCCM Target Sputter Clean Time: 15 Minutes SWR During Deposition: 1.5
29	Spin Resist	Resist: AZ P4210 Resist Type: Positive Spin Speed: 4000 rpm Spin Time: 30 secs
30	Bake	Bake Temperature: 100 °C Bake Time: 90 secs
31	Hacker Fab Maskless Litho Stepper	Exposure time: 8 secs
32	Develop	Developer: AZ 400K : DI Water (1:3) Develop Time: 30 secs
33	Wet-Etch	Etch Time: 8 mins Etching Agent(s): Type A Al Etch (PAN) Etch Temperature: 40 °C
34	Wet Strip Resist	Stripping Agent(s): Acetone then IPA Blow dry with N2 gun after.
35	Spin-Coat	Material Type: Non-Resist Material: 700B (spin on glass) Spin Speed: 4000 rpm Spin Time: 20 secs
36	Bake	Bake Temperature: 400 °C Bake Time: 10 mins
37	Spin-Coat	Material Type: Adhesion Promoter Material: HMDS Spin Speed: 4000 rpm Spin Time: 30 secs
38	Bake	Bake Temperature: 100 °C Bake Time: 60 secs
39	Spin Resist	Resist: AZ P4210 Resist Type: Positive Spin Speed: 4000 rpm Spin Time: 30 secs
40	Bake	Bake Temperature: 100 °C Bake Time: 90 secs
41	Hacker Fab Maskless Litho Stepper	Exposure time: 8 secs
42	Develop	Developer: AZ 400K : DI Water (1:3) Develop Time: 30 secs
43	Wet-Etch	Etch Time: 20 secs Etching Agent(s): 6:1 BOE
44	Wet Strip Resist	Stripping Agent(s): Acetone then IPA Blow dry with N2 gun after.
45	Sputter w/ CMU Hacker Fab RF Sputtering Chamber	Material: Al Film thickness: 300 nm Deposition Rate: 2.5 Å/s Deposition Time: 120 mins Sputter Type: RF Sputtering RF or DC Power: 100 Watts Sputter Gas Composition: 15 SCCM UHP Ar Chamber Pressure: 3E-3 Torr Throw Distance: 3" Base Pressure Pre Deposition: 1E-7 Torr Target Sputter Clean Ar Flow: 30 SCCM Target Sputter Clean Time: 15 Minutes SWR During Deposition: 1.5
46	Spin Resist	Resist: AZ P4210 Resist Type: Positive Spin Speed: 4000 rpm Spin Time: 30 secs
47	Bake	Bake Temperature: 100 °C Bake Time: 90 secs
48	Hacker Fab Maskless Litho Stepper	Exposure time: 8 secs
49	Develop	Developer: AZ 400K : DI Water (1:3) Develop Time: 30 secs
50	Wet-Etch	Etch Time: 4 mins Etching Agent(s): Type A Al Etchant (PAN)
51	Wet Strip Resist	Stripping Agent(s): Acetone then IPA Blow dry with N2 gun after.

#### MOSFET example masks and images {% stepper %} {% step %} ### pattern and etch alignment marks into Si

{% endstep %} {% step %} ### spin on glass (dopant mask), pattern and etch source/drain regions

{% endstep %} {% step %} ### spin on dopant, diffuse

{% endstep %} {% step %} ### etch/clean off dopant, sputter gate films, pattern and etch gates

{% endstep %} {% step %} ### spin on glass, pattern and etch contact holes

{% endstep %} {% step %} ### sputter Al, pattern and etch contact pads

{% endstep %} {% endstepper %} All curves below are recorded from lower row (50 um gate length, 21.4 um channel length) #### NMOSFET Electrical Results - reactively sputtered gates from Al target reactively sputtered gate **pre anneal and post anneal** electrical testing

Chip/Processing	On Current Vd=5, Vg=0 (A)	Off Current Vd=5, Vg=0 (A)	On/Off Ratio Vd = 5	Gate Leakage at Vg=Vd=5V (A)
pre anneal	4.4E-4	1.2E-6	369	1.45e-7
400C open air anneal	4.9E-4	2.2E-6	227	4e-5

#### PMOS and NMOSFET Electrical Results - non reactive sputtered gates from Al2O3 target. The following devices used a "triple mask" during diffusion, so steps 12-13 from the MOSFET process flow above were replaced by 3 consecutive spin coating and baking steps of 700B. Bakinf done in tube furnace 1100C for 60s for full densification. The following devices also used a gate oxide sputtered form an Al2O3 target, with 1% O2 flow, then a thermally evaporated Al gate. So steps 27-28 from the MOSFET process flow above were replaced by the following... |

RF Sputtering with Al2O3 target, 1% O2, 99% Ar, 20sccm totla flow
30nm thick Al2O3

| | -------------------------------------------------------------------------------------------- | ------------------------------------------------------------------- | |

Al Thermal Evaporation
300nm thick Al

| The NMOS also had step 24 modified to be 5 min at 1100C instead of 30min. The PMOS chip had step 22 modified to use B154 the Boron SOD from filmtronics. Additionally step 24 modified to be 5 min at 1000C due to higher mobility of Boron. PMOS and NMOS Images and Testing Results

Chip	On Current Vd=5, Vg=0 (A)	Off Current Vd=5, Vg=0 (A)	On/Off Ratio Vd = 5	Gate Leakage at Vg=Vd=5V (A)
PMOS	2.45e-4	3.96e-7	617.9	9e-10
NMOS	1.5e-3	5.6e-5	26.3	1.2e-8

#### TLM Structures (contact resistance and sheet resistance results) Built on same chip as reactively sputtered gate FETs

| Processing | Specific contact resistance (ohm-cm^2) | Sheet Resistance (ohm/square) | | -------------------------------------- | -------------------------------------- | ----------------------------- | | Chip 1 "maskless doping" | 7.15E-4 | 56.32 | | Chip 2 "masked doping" | 1.78E-3 | 113.25 | | Chip 2 "masked doping" - 400C annealed | 3.75E-4 | 92.27 | ## n well process development As explained above, the CMOS process requires both a gate oxide deposition process, and the ability to create n type wells within the p type substrate. As seen in the CMOS diagram below, the PMOS transistors sit inside the n wells. This section documents the process development for creating the n type wells for the PMOS transistors on a CMOS chip. Controlling the n well donor concentrations is key for threshold voltage (Vt) control, and controlling the n well depth is key to ensure the PMOS devices stay isolated from the p type body.

The NMOS transistors in the previous section were fabricated on Boron doped (p-type) 5-10 ohm-cm resistivity. As per the plot below and [BYU resistivity calculator](https://cleanroom.byu.edu/resistivitycal), 5-10 ohm-cm corresponds to \~2E15 Boron atoms/cm^3 (assuming all B are acting as substitutional atom defects in the Si lattice, interstitial Boron atoms do not behave as nice acceptors)

[Modern Semiconductor Devices for Integrated Circuit](https://www.chu.berkeley.edu/modern-semiconductor-devices-for-integrated-circuits-chenming-calvin-hu-2010/) Figure 2-8
This Boron concentration in the NMOS channel is much lower than the Phosphorous concentration at the Si surface in the NMOS source/drain regions, which are degenerative doped to high concentrations. Degenerative doping means that the fermi level has shifted into the conduction or valence band (conduction band in the Phosphorus case) such that the Si acts like a metal. This is best observed in the figure below, showing that the fermi level is essentially at the conduction or valence band when donor or acceptor concentrations reach \~1E20 /cm^3

[Modern Semiconductor Devices for Integrated Circuit](https://www.chu.berkeley.edu/modern-semiconductor-devices-for-integrated-circuits-chenming-calvin-hu-2010/) Figure 1-12
In contrast to the source/drain regions, the dopant concentration in the channel needs to be much lower in order to control the FET’s flatband voltage (Vfb) and more importantly the Vt. By using the below equations from [Modern Semiconductor Devices for Integrated Circuits ](https://www.chu.berkeley.edu/modern-semiconductor-devices-for-integrated-circuits-chenming-calvin-hu-2010/)by Chenming Hu, we can plot the expected Vfb and Vt for different Boron concentrations, assuming we have a 20 nm Al2O3 film with dielectric constant of 6 and an Al gate contact (relevant example based on the MOS devices in above sections).

[Modern Semiconductor Devices for Integrated Circuit](https://www.chu.berkeley.edu/modern-semiconductor-devices-for-integrated-circuits-chenming-calvin-hu-2010/) Assuming no charge in the oxide (no defects or impurities) gate work function is known from the experimental work function of the gate metal (Al in our case, \~4.1 eV). The semiconductor/Si work function is calculated from the Si electron affinity, conduction band energy, and the fermi level. And the fermi level is dependent on dopant type and concentration.
Vt is calculated from the equation below where Vt is dependent on Vfb, dopant type/concentration, and oxide capacitance. The oxide capacitance is determined from our CV testing results showing k=4 at t = 20nm. Na is acceptor concentration, Phi is the bulk potential which is based on Na, Epsilon is Si permittivity, q is elementary charge.

[Modern Semiconductor Devices for Integrated Circuit](https://www.chu.berkeley.edu/modern-semiconductor-devices-for-integrated-circuits-chenming-calvin-hu-2010/)
With these equations used in a python script we can plot Vfb and Vt against doping concentration to determine what doping concentration range we would need to achieve in the n well to have functioning PMOS devices. The NMOS case is also plotted to review the choice of 5-10 ohm p type wafers.
{% file src="/files/DhvFrPfoLbO0olRrzbyx" %}

As seen above, Vt is much more sensitive to dopant concentration than Vfb. Based on the plots, we see that the Boron concentration 2E15 should give a Vfb of -.826V and a Vt of -0.117V. A negative prediction for Vt means that 5-10 ohm wafers are probably not the right choice if we want to minimize off current when Vg = 0.
If we make this same plot but assume an n type phosphorus doped channel, we see that careful donor concentration control is required for a reasonable Vt. Donor is specified, since the background Boron counteracts the donor effects of the P, ie Nd = N\_Phosphorous - N\_Boron.

The key takeaway from this plot is that dopant concentration in the n well must be at least below 10^18 atoms/cm^3 to achieve a Vt low enough for reasonable demonstration of PMOSFETS within a P type substrate. Too high of a P concentration will require Vt’s that may approach the breakdown voltage of the gate or SMU Voltage limit. For this reason, the next natural step in process development is to develop a doping process that is capable of achieving low P concentration in the n-well. #### So how do we make the n well? Spin on diffusants from Filmtronics are used for the source/drain doping in the Hacker Fab self aligned NMOS process, and the NMOS/PMOS devices demonstrated above which use the Al2O3-Al gate. The goal of this part of the project is to also use the spin on dopants for creating the n well to keep the required tooling and chemicals as cheap and simple as possible. To do this, the common method of predeposition diffusion with a surface dopant source followed by drive-in diffusion in the absence of a dopant source is used, outlined below.

Step	Cross section	Diffusion profile
Apply spin on dopant No new dopants introduced
“Predeposition diffusion” Use moderate to high temperatures with a dopant source present at the surface. In this case Filmtronics P504 Phosphorus spin on dopant. Ficks laws are solved assuming a semi-infinite body and constant surface source. Cs is surface concentration Dopant profile follows error function shape.
Remove dopant source, deposit SiO2 to prevent excess oxidation in the following step.
“Drive in diffusion” High temperatures with no dopant source present. Ficks laws are solved assuming a semi-infinite body and limited dopant dose near the surface. Q is the dopant dose left from the predisposition diffusion. (integrate predep profile) Dopant profile follows Gaussian shape.

\
Provided is the python script used for modeling this diffusion based on a multistep process, where each step can be defined as having dopant present or not (ie predeposition or drive in). {% file src="/files/RVvF4MpXxHgNTSamdZS3" %} The script assumes multiple constants based on Literature for P and B diffusion in Si... * Surface solubility (input for Cs) * The surface solubility is actually what is supposed to define Cs in the diffusion equations, instead of the actual concentration of the spin on dopant source. Surface solubility of P or B at various temperatures is usually much lower than the actual concentration in a spin on dopant. * “[Spin-on dopant technology for cost-effective source/drain formation in silicon MOSFET](https://www.sciencedirect.com/science/article/pii/S003811012500142X)s” reports a concentration vs depth plot of SOD treated wafers measured via SIMS, indicating the surface solubility of P in Si is about **1e20 /cm^3** between 800-900C, even though the SOD P concentration is \~1e22 /cm^3. * Activation Energy (Ea) and Diffusivity constant pre-exponential (D0) * Phosphorous in Si. * "[On phosphorus diffusion in silicon under oxidizing atmospheres](https://www.sciencedirect.com/science/article/pii/0038110173900567)" Measures D and reports **Ea of 2.5 eV**. Basedon this D0 can be calcuated to be **3.72E-4 cm^2/s**. This is for an atmosphere of N2 w/ 10% O2, which is the closest to air composition that they studied (tube furnace used in Hacker Fab @ CMU is opne air) * Boron in Si * [This textbook](https://www.cityu.edu.hk/phy/appkchu/AP6120/8.PDF) reports D0 = .76 cm^2/s and Ea = 3.46. "[Solid Solubility and Diffusion Coefficients of Boron in Silicon](https://iopscience.iop.org/article/10.1149/1.2412239/pdf)" reports different values which could be substituted instead. Below is the script output comparing a 5 min 800C predeposition and a 600C 1 min predisposition profile, both with 1100C 1 hour drive in. The model suggests that 800C for 5 min predep is implanting too much dosage to reach the doping targets, and that 600C for 1 min does achieve the target concentration. However, basic multimeter resistance measurements tests at various diffusion temps showed little to no diffusion occurring below 800C. So, 800C 5 min predeposition was chosen for experimental testing.

The plot below would correspond to a p type S/D region within the n well. The model predicts that a 1000C 5 min predisposition diffusion of Boron would keep the p type region within the n well. As seen by the junction depth of the p region being well within the n well junction depth.

The model is likely far off from reality given these parameters so it is mainly just a guide to see generally what predep and drive in times/temps would be appropriate to help narrow down the recipe. The general lesson from playing with the modeling script is that the initial dosage of dopant is the most sensitive knob for tuning the surface contraction after drive in, whereas drive in time has diminishing effects. These same takeaways can be inferred just from the equations governing the predep and drive in profiles. The 600C finding form the diffusion model seemed too low So, I first employed hot probe testing for 5 min doping at various temps to detect when the surface doping type switches. The hot probe method is a common way to measure whether a semiconductor is n or p type. It relies on a heated and room temp probe connected to voltmeter. The hot probe causes a diffusion current of electrons or holes between probes, and a - or + voltage is measured depending on if the dominant charge carriers are holes or electrons.

Hot probe test setup using a soldering iron and hand held multimeter. In this configuration p type Si reads +V and n type Si reads -V.

Undoped 5-10ohm p type wafer resistance measures \~400 KOhm with handheld multimeter. The issue with the hot probe test is the sampling depth compared to the junction depth. The heat from the probe incites diffusion deep into the wafer, whereas the doping type may have only been switched in within the first couple of micrometers or less. The resistance drops after just the 800C diffusion, but the hot probe only shows a dopant reversal at 950C diffusion, which indicates that the p type wafer surface may actually have been reversed to n type, but the hot probe test is being dominated by the substrate instead of the surface. The resistance drop at 800C (compared to a p type wafer having undergone no diffusion) is enough to signal that a meaning phosphorous dose has been delivered near the surface of the wafer. #### Determination of Dopant concentration with CV Measurement Without techniques like Secondary Ion Mass Spectrometry, dopant concentration near the surface of the n well can still be measured just through Capacitance-Voltage testing of MOSCaps. This is done by plotting 1/C^2 against voltage, and measuring the slope in depletion mode. The slope is then used to calculate acceptor or donor concentration via the relation below.

[Tektronix CV Applications Guide](https://www.tek.com/en/documents/application-note/c-v-testing-semiconductor-components-and-devices-applications-guide) It is important to note, that acceptor/donor concentration is what's calculated, not the actual concentration of Phosphorus or Boron. They can be different, since the P directly counteracts the underlying Boron doping, and if the P does not end up on a substitutional site it may not act as a donor. This may explain some discrepancy between the modeled and experimentally measured values for donor concentration seen below. The plot below demonstrates the measurement technique applied to MOSCaps fabricated on the 5-10ohm p type wafers. Both C and 1/C^2 axes are plotted to clarify what region of the CV plot was used for calculating the donor/acceptor concentrations. {% file src="/files/tSncAX6ndQToVy4iOh59" %}

The plot below shows the doping concentration calculation for n type 1-10 ohm wafer with no diffusion as well as one with 5 min 800C predep + 1100C 1 hour drive in (on n type wafer). The choice of testing the diffusion conditions on an n type wafers was purposeful. If p type wafers were used, the n well would also create a conjunction in series with the MOSCap which can distort the CV measurement, so n type wafers were used as the starting substrate.

| Sample | Expected concentration (N) | Measured concentration (N) from MOSCap CV | | ---------------------------------------------------------------- | ------------------------------------------------------------------------------ | ----------------------------------------- | | p type 5-10 ohm wafer | 2e15 /cm^3 based on [BYU calculator](https://cleanroom.byu.edu/resistivitycal) | 1.71e15 /cm^3 (acceptors) | | n type 1-10 ohm wafer | 1e15 /cm^3 based on [BYU calculator](https://cleanroom.byu.edu/resistivitycal) | 1.08e15 /cm^3 (donors) | | 800C 5min predep + 1100C 1hr drive in (on n type 1-10 ohm wafer) | 9.5e17/cm^3 based on diffusion model above | 2.05e16 /cm^3 (donors) | The measurement shows that the 800c 5 min predep with 1100C 1hr drive in yields 2.05e16 /cm^3 donor concentration, which should yield a Vt of \~1.2V based on the Vt vs N calculations. Next step is tuning the PMOS S/D p type regions to remain isolated and within the n well. ## Appendix #### 9:9, 3hr, Standard RCA Clean

| size (area) | frequency | area\_mm2 | k\_avg\_raw | k\_slope\_avg\_raw | Vfb\_PN\_avg\_raw | Vfb\_NP\_avg\_raw | deltaVfb\_avg\_raw | k\_avg\_corrected | k\_slope\_avg\_corrected | Vfb\_PN\_avg\_corrected | Vfb\_NP\_avg\_corrected | deltaVfb\_avg\_corrected | Gpeak\_PN\_S | Gpeak\_NP\_S | Rs\_mean\_ohm | | ----------------- | --------: | --------: | ----------: | -----------------: | ----------------: | ----------------: | -----------------: | ----------------: | -----------------------: | ----------------------: | ----------------------: | -----------------------: | -----------: | -----------: | ------------: | | Small (0.2 mm²) | 10KHz | 0.20 | 5.725439 | 3.625706 | -3.35 | -4.30 | 0.95 | 10.969794 | 3.796601 | -3.20 | -4.55 | 1.35 | 0.000007 | 0.000026 | 4665.743838 | | Small (0.2 mm²) | 100KHz | 0.20 | 4.742700 | 2.765370 | -4.35 | -4.70 | 0.35 | 5.292607 | 3.124594 | -4.15 | -4.45 | 0.30 | 0.000081 | 0.000090 | 910.056283 | | Small (0.2 mm²) | 1MHz | 0.20 | 2.901555 | 0.793532 | -4.75 | -4.95 | 0.20 | 4.029582 | 2.940564 | -4.65 | -4.85 | 0.20 | 0.000823 | 0.000622 | 273.774244 | | Medium (0.79 mm²) | 10KHz | 0.79 | 4.972657 | 3.625706 | -3.15 | -4.30 | 1.15 | 5.803228 | 3.796601 | -2.95 | -3.70 | 0.75 | 0.000029 | 0.000053 | 2254.233872 | | Medium (0.79 mm²) | 100KHz | 0.79 | 3.760431 | 2.765370 | -4.50 | -4.75 | 0.25 | 4.186907 | 3.124594 | -4.30 | -4.55 | 0.25 | 0.000289 | 0.000286 | 309.539446 | | Medium (0.79 mm²) | 1MHz | 0.79 | 1.665962 | 0.793532 | -4.75 | -4.95 | 0.20 | 3.416144 | 2.940564 | -4.80 | -5.00 | 0.20 | 0.002619 | 0.001648 | 137.554599 | | Large (1.77 mm²) | 10KHz | 1.77 | 3.918623 | 3.625706 | -3.10 | -4.35 | 1.25 | 4.620144 | 3.796601 | -3.05 | -3.90 | 0.85 | 0.000062 | 0.000073 | 1385.010681 | | Large (1.77 mm²) | 100KHz | 1.77 | 3.022550 | 2.765370 | -4.30 | -4.65 | 0.35 | 3.404616 | 3.124594 | -4.10 | -4.50 | 0.40 | 0.000523 | 0.000518 | 210.306410 | | Large (1.77 mm²) | 1MHz | 1.77 | 1.054850 | 0.793532 | -4.35 | -4.65 | 0.30 | 3.077261 | 2.940564 | -4.65 | -4.90 | 0.25 | 0.005672 | 0.003891 | 97.212422 | --- # Agent Instructions This documentation is published with GitBook. GitBook is the documentation platform designed so that both humans and AI agents can read, navigate, and reason over technical content effectively. Learn more at gitbook.com. ## Querying This Documentation If you need additional information that is not directly available in this page, you can query the documentation dynamically by asking a question. Perform an HTTP GET request on the current page URL with the `ask` query parameter, and the optional `goal` query parameter: ``` GET https://docs.hackerfab.org/home/processes/cmos-sputtered-gate-stack-wip.md?ask=&goal= ``` `ask` is the immediate question: it should be specific, self-contained, and written in natural language. `goal` is optional and describes the broader end goal you are ultimately trying to accomplish on behalf of the user. GitBook uses it to tailor the answer towards what is most useful for that goal. The response will contain a direct answer to the question and relevant excerpts and sources from the documentation. Use this mechanism when the answer is not explicitly present in the current page, you need clarification or additional context, or you want to retrieve related documentation sections.