# NMOS - Polysilicon Resistors (WIP)
A polysilicon resistor process flow fully compatibile with the Self Aligned NMOS process. Designed to be useful in building NMOS logic circuits.
## Background
Without a viable way to fabricate PMOS, the logic is limited to an NMOS-only design. Unlike CMOS logic, which employs PMOS transistors to switch the voltage from High to Low, NMOS logic uses a resistive load in to pull the voltage low.
In the basic example of an NMOS inverter, the circuit is essentially a voltage divider. When the NMOS is off, there is 0 voltage drop across the resistor and Vout = VDD. When the NMOS is on, current flows to ground and Vout is pulled low. While digital logic is relatively robust in terms of HI/LO cutoff voltage requirements, the pull-up resistive load should be large compared to the channel resistance when the NMOS is on. A direct consequence of this design is that NMOS logic has the disadvantages of slow RC switching time and higher power consumption.
The poly resistor process used in our project was designed as a derivative of the existing NMOS process, rather than a completely independent fabrication flow. Even though we already had an established substrate resistor process, the low sheet resistance prompted us to look for a better material for fabricating pull-up resistors.
In this resistor process, the doping time is reduced compared to the NMOS process to increase the resistance of the polysilicon layer for use as resistor pull-ups. A higher resistance polysilicon layer is also attractive in any future integrated processes because it can help reduce unwanted leakage paths and preserve clearer separation between intentionally resistive elements and highly conductive transistor regions.
## Tools
Same as the self-aligned NMOS process.
## Procedure
[Fabublox link](https://www.fabublox.com/process-editor/581d616b-fd7d-4b0c-b464-549f8c002721)
[Resistor Masks](https://docs.google.com/presentation/d/1PqgsMFEELReuOm6cnJ8Q5tTdDkawcxXL/edit?slide=id.g3d2d9defb61_2_281#slide=id.g3d2d9defb61_2_281)
Uses thes same wafer as the Self-Aligned NMOS process. Includes the same steps with the exception of adjusted first diffusion time.
| Step # | Step Name | Parameters | Comments | Layer Stacks |
| ------ | ---------------------------- | ------------------------------------------------------------------------------------------------------------------------------------------------ | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| 0 | Substrate Stack | PolySi: 500 nm
SiO2: 20 nm
Si (lightly p doped): 525 µm
| Same Wafer as NMOS Process |  |
| 1 | Acetone + IPA Clean (N2 dry) | Cleaning Agent: Acetone then IPA | Squirt with Acetone, then IPA, then dry the surface with the N2 gun. |  |
| 2 | Spin-On Dopant | Spin-On Dopant Name: P504
Dopant Type: N
Spin Speed: 4000 rpm
Spin Time: 20 secs
| P504 from Filmtronics
must use filtered syringe tips
|  |
| 3 | Bake | Bake Temperature: 200 °C
Bake Time: 10 mins
| |  |
| 4 | Dopant Diffusion | Diffusion Time: 5 mins
Diffusion Temperature: 1100 °C
Environmental: false
| In tube furnace with fused quartz tube |  |
| 5 | Wet-Etch | Etch Time: 10 mins
Etching Agent(s): 6:1 BOE
Etch Temperature: 25 °C
| BOE is HF + Ammonium Fluoride
DI water rinse after etch
|  |
| 6 | Acetone + IPA Clean (N2 dry) | Cleaning Agent: Acetone then IPA | Squirt with Acetone, then IPA, then dry the surface with the N2 gun. |  |
| 7 | HMDS Vapor Prime | Deposited Monolayer: HMDS
Layer Thickness: 5 Å
| Not Using an actual vapor primer.
Bake @ 120C for 30S to dehydrate
Spin @ 3000 rpm for 20 s
Bake @ 120C for 60S to drive off excess
|  |
| 8 | Spin Resist | Resist: AZ P4210
Resist Type: Positive
Spin Speed: 4000 rpm
Spin Time: 30 secs
| |  |
| 9 | Bake | Bake Temperature: 100 °C
Bake Time: 90 secs
| |  |
| 10 | Stepper Lithography | | Pattern 1 -Defining Gates |  |
| 11 | Develop | Developer: AZ 400K 3:1 (DI water : developer)
Develop Time: 30 secs
Develop Temperature: 25 °C
| Develop time may vary, use current stable patterning process. Modulate exposure time and develop time as needed to achieve good pattern resolution |  |
| 12 | ICP-RIE | Etch Time: 90 secs
Etch Gas Composition: SF6
Gas Flows and Ratios: 10 sccm
RF Power or Voltage: 100 Watts
Sidewall Angle: 0 °
| Place around 1/3 from the back of the chamber |  |
| 13 | Wet Strip Resist | Stripping Agent(s): Acetone then IPA | Squirt with acetone, then IPA, then dry with N2 gun |  |
| 14 | Plasma Descum | Gas composition: O2 10 SCCM
RF Power: 100 Watts
Time: 2400 secs
| Alternatively, a shorter clean can be done before resist strip. |  |
| 15 | Dopant Diffusion | Diffusion Time: 30 mins
Diffusion Temperature: 1100 °C
Environmental: false
| |  |
| 16 | Spin-Coat | Material: 700B
Spin Speed: 4000 rpm
Spin Time: 20 secs
| 700B from filmtronics |  |
| 17 | Bake | Bake Temperature: 200 °C
Bake Time: 10 mins
| |  |
| 18 | Acetone + IPA Clean (N2 dry) | Cleaning Agent: Acetone then IPA
Ultra-Sonication: false
| Squirt with Acetone, then IPA, then dry the surface with the N2 gun. |  |
| 19 | HMDS Vapor Prime | Deposited Monolayer: HMDS
Layer Thickness: 5 Å
| Not Using an actual vapor primer.
Bake @ 120C for 30S to dehydrate
Spin @ 3000 rpm for 20 s
Bake @ 120C for 60S to drive off excess
|  |
| 20 | Spin Resist | Resist: AZ P4210
Resist Type: Positive
Spin Speed: 4000 rpm
Spin Time: 30 secs
| |  |
| 21 | Bake | Bake Temperature: 100 °C
Bake Time: 90 secs
| |  |
| 22 | Stepper Lithography | Exposure time: 8 secs | Pattern 3 - Defining Al contact areas |  |
| 23 | Develop | Developer: AZ 400K 3:1 (DI water : developer)
Develop Time: 60 secs
Develop Temperature: 25 °C
| Develop time may vary, use current stable patterning process. Modulate exposure time and develop time as needed to achieve good pattern resolution. |  |
| 24 | Wet-Etch | Etch Time: 20 secs
Etching Agent(s): 6:1 BOE (HF)
| |  |
| 25 | Wet Strip Resist | Stripping Agent(s): Acetone then IPA | Squirt with acetone, then IPA, then dry with N2 gun |  |
| 26 | Thermal Evaporation | Film thickness: 500 nm | Alternatively sputtering can be used depending on available lab tooling. |  |
| 27 | Acetone + IPA Clean (N2 dry) | Cleaning Agent: Acetone then IPA
Ultra-Sonication: false
| Squirt with Acetone, then IPA, then dry the surface with the N2 gun. |  |
| 28 | Spin Resist | Resist: AZ P4210
Resist Type: Positive
Spin Speed: 4000 rpm
Spin Time: 30 secs
| |  |
| 29 | Bake | Bake Temperature: 100 °C
Bake Time: 90 secs
| |  |
| 30 | Stepper Lithography | | Pattern 4 - Interconnect and contact pad definition |  |
| 31 | Develop | Developer: AZ 400K 3:1 (DI water : developer)
Develop Time: 60 secs
Develop Temperature: 25 °C
| Develop time may vary, use current stable patterning process. Modulate exposure time and develop time as needed to achieve good pattern resolution. |  |
| 32 | Wet-Etch | Etch Time: 5 mins
Etching Agent(s): Type A Al Etchant
Etch Temperature: 40 °C
New Field 1: stir speed 150 rpm
| Heat Etch up for 5-10 minutes before begining. Di water rinse after etch.
Etch rate to be around 90nm/minute with Type A Al etchant for the Evaporatied Al, and based off the evaporator QCM readings.
|  |
| 33 | Wet Strip Resist | Stripping Agent(s): Acetone then IPA | Squirt with acetone, then IPA, then dry with N2 gun |  |
## Results
| L × W (μm) | L/W | Valid samples | Mean Rdiff (kΩ) | Avg Sheet Resistance (kΩ/sq) |
| --------------- | ---- | ------------- | --------------- | ---------------------------- |
| 247.86 × 32.40 | 7.65 | 4 | 15.91 | 2.08 |
| 247.86 × 65.34 | 3.79 | 3 | 15.15 | 3.99 |
| 247.86 × 131.76 | 1.88 | 3 | 4.63 | 2.46 |
| 165.24 × 82.08 | 2.01 | 2 | 13.15 | 3.42 |
| 247.86 × 82.08 | 3.02 | 2 | 21.15 | 2.13 |
| 331.02 × 82.62 | 4.01 | 3 | 19.71 | 2.79 |
| 413.64 × 82.08 | 5.04 | 3 | 16.43 | 2.03 |
The per-resistor table shows that resistance increases mainly with longer effective length and decreases with larger width, as expected from the sheet-resistance model. The horizontal and vertical structures are broadly consistent, but the spread between nominally similar geometries suggests that contact non-ohmic behavior, geometry extraction uncertainty, and process variation are still significant. Using the 4 V bias point gives a practical operating-point estimate of sheet resistance, but it should be treated as a bias-specific effective sheet resistance, not a fully geometry-independent material constant.
### Images
#### Step 11: Resistor Body Pattern
#### Step 24: Resistor Contacts Pattern
#### Step 31: Probing Contacts Pattern
### Appendix
5 Min Dopant Diffusion, Length modulation w/ width = 82 µm
{% file src="/files/uR7OZ0Xxzq3gGf2lmBTT" %}
{% file src="/files/KtzYRFzUsIlranWjIGzI" %}
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