• They normally have one

"I am trying to attach ___ to ____, what can i use?"

Right now we use factories and tools that are optimized to manufacture at scale to do our integrated circuit prototyping. There does not exist a set of machines that enable rapid tape-out of semiconductor devices on a budget, nor are there sufficient resources to make/modify fab tools from the ground up.

Nanofabrication is often communicated as complex magic, where every machine is immutable. We believe that innovation in the industry requires a thorough understanding of these machines from first principles, which will lead us to simpler solutions. Even on machines and processes of magnitudes less complexity than modern industry, there are designs worth sharing.

The use of low-cost, abundant, and fast-turn-around hardware serves a larger purpose than making the fab cheaper. These design constraints are what enable others to recreate, modify, and contribute to our work. The simpler the better.

working on the hacker fab.

You don't need prior nanofabrication experience to create meaningful contributions.

You do need to read the Required Reading.

You don't need to recreate the entire fab to contribute, although you can.

We communicate entirely over Discord.

this website.

This page is a home for all shared documentation. There are enough resources here to turn an empty room into one that fabricates simple IC's in a matter of months.

Many pages are works-in-progress. It is natural for individual contributors' work-in-progress notes to exist on google drive, notion, etc. Links to these exist at the top of each page, however these notes move to Gitbook as soon as possible.

Any contributor can submit change requests with a free Gitbook account. All of this is on Github, but formatted nicely here on Gitbook. You can contribute directly through Github as well.

For the most up-to-date status on everything, join the Discord.

fab toolkit.

Here is a list of all the tools built or bought necessary to make our devices.

Every build contains:

• BOM

• Links to Design Files

• Links to Code

• First Principles Understanding of Machine Design (WIP)

fabrication tools.

verification / metrology tools.

chemicals.

background and licensing.

The Hacker Fab was inspired by Sam Zeloof.

The Hacker Fab was started by Elio Bourcart, Alexander Hakim, and Sam Zeloof.

The first Hacker Fab was opened at Carnegie Mellon University, and currently managed by Matthew Moneck, Tathagata Srimani, and Jay Kunselman.

The Hacker Fab is run entirely by independent contributors.

By default, contributions use the following license stack, but may carry an additional NOTICE file depending on the origin of the contribution.

The tube of the furnace is a 2” diameter quartz class tube with 5mm thickness, wrapped in about 3 layers of ceramic wool and held together with metal zip ties. Wrapped around the glass tube is 24g double twisted kanthal wiring, held in place with refractory cement. Surrounding this is a tube of sheet metal held by sheet metal screws and two metal end caps with holes cut through to allow access to the tube and for the wiring to stick out. A stand and handle made out of sewer pipe brackets is included in the design, and attached to the stand is a bracket with a plastic wiring box to act as a space to attach the PID controller, PID relay, and fuse reset. The kanthal wiring that extends beyond the tube is folded in half lengthwise (thickness of 4 24g kanthal wires) and covered in a ceramic weave tube for insulation. The wiring used for the PID and associated devices are recycled wires from an old chandelier, coated in a rubber insulation. Heat resistant tape is used to protect the wires in places where needed. A thermocouple is attached to the PID controller and inserted in the furnace. The furnace is wired to an extension cord and plugged into a programmable circuit breaker to protect the main power grid.

3. Materials

Sheet metal, kanthal wire, refractory cement, ceramic wool, quartz glass tube, nuts and bolts, sewer pipe brackets, ceramic weave wire insulation, motor control, thermocouple, heat resistant tape, voltmeter, programmable circuit breaker, handle, PID controller, PID relay, plastic circuit box, metal bracket, rivets, metal zip ties, fuse reset, metal end caps

4. Construction

1. Coat mid section of glass tube in refractory cement, score lines to allow for shrinkage during curing, let cure for several hours

2. Measure kanthal wire using the desired number of loops around the tube, with some extra length, then double the total length. Fold in half and twist the entire wire tightly using a power drill and tension. Carefully wrap wire around the cemented area of the tube, holding firmly. Hold with rubber bands and cement on top, let cure.

3. Wrap tube with wire in 3 layers of ceramic wool. Bend the twisted kanthal wiring in half to increase resistance and extend to fit where the hole sites in the casing would be. Use ceramic weave insulation and heat resistance tape. to prevent contact between wiring and the casing.

4. Bend sheet metal into a tube and secure together with screws or rivets. Drill holes to allow for wiring to come through the casing. Drill 2” holes through the end caps and secure to the tube furnace with sheet metal screws.

5. Screw on stand, add bracket with holes to the stand and screw the plastic circuit box to the bracket. Pull insulated kanthal wires into the box and wire PID controller, relay, fuse reset, and thermocouple.

5. Testing and performance

• Hit the energy and temperature requirements

• Still functional after may test runs

• Failings with the PID controller, requires the use of the motor control to control the current and prevent the furnace wires from overheating, additionally requires the use of a lightbulb to kickstart the motor control into drawing power and heating using the PID is inconsistent due to the jumps in current.

• Despite this, when the current is controlled with the motor control, the PID controller works effectively in maintaining a specific heat in the furnace

6. Things to improve on

• Need to figure out circuit configuration to power furnace without use of light bulb

• Need to figure out how to control current without motor control (for simplicity)

• Need to figure out insulation problem for wires to prevent them from becoming too hot

Device Physics Overview (30 min)

• Electrons, bandgap, etc.

Before we had transistors, we had lightbulbs (18 min)

• Then we moved to silicon

• This stuff is regularly communicated as complex magic, and requires the permission of billionaires to work on it. We are starting from 1960’s level complexity and working our way up to modern complexity.

The creation of the blue LED (30 min)

• Extremely well told story of the man who figured out how to manufacture blue LEDs

• We are not the first people to claim that innovation in the semiconductor industry requires intimate knowledge of the fabrication tools

Fabublox (∞)

• A fantastic tool being developed by friends at MIT. Overview of many processes, with each being a linear recipe

• Make an account, and go to “fabubase” in menu

• Check out our Hacker fab process, as well as others

• Go through and try to recreate our process from scratch without cheating. See how far you get, and write down things that don’t make sense (1 hour)

How do these things even make computers?

• How we turn sand to intelligence

• Making logic gates from transistors (13 min)

Transistor → logic gates → basic logic circuitry (timers, counters, latches, shift registers, etc.) → architecture abstractions that people made up over decades → CPU

TinyTapeout Video Example: Making ASIC

• Application Specific Integrated Circuits

Not all transistors are created equal

Below: ideal transistor IV curve vs. our first curves.

These both exhibit transistor-like characteristics. Looking back at the Veritasium video about how the first computers were made with lightbulbs - a transistor really boils down to a repeatable switching action. When we look at our curve on the right, we see multiple issues:

• The curves don’t go through the origin, they start with a voltage offset

  • This means that when we apply a voltage to the gate (open the valve to allow current through), current doesn’t run through the drain to the source until we apply ~3V to the drain/source connection.

• The lines are all squiggly?

So we try to debug this by finding literature that debugged something similar, or often we simply design and run more experiments. Skim through pages 172-176 (bottom corner number, not pdf page number) of this document. Their transistors have very similar issues to ours. When you read this document, the answers are behind a huge layer of jargon and acronyms that make the barrier to entry for understanding extremely high.

In reality here is what it is saying:

• Our source-drain is dominated by an aluminum metal-to-silicon Schottky junction instead of doping

Put simply, we just directly connected an electrical characteristic (IV curve) to a physical process parameter. We now have an exact experiment to try over the next week:

• Less metal annealing

• More Si02 etch before metal deposition (to ensure metal contacts Si instead of SiO2)

Right now it takes about 8 hours of work + waiting overnight to turn a blank wafer into one with NMOS transistors on it. Then we go to the probe station, test it, organize the data, look at the graphs, and think. That’s how long it takes to verify each new experiment. With each machine, script, or management tool we create, we push to significantly decrease this iteration cycle.

We've only made NMOS devices so far, but there are so many more things to be made. That means our process data corresponds to NMOS only, but most process steps can be generalized to any process if documented properly.

Each unique device can also use different materials entirely, which requires different machines.

• What metal are we depositing?

• What does the doping profile look like?

• etc.

The ideal goal for the Flame furnace would be to reach 1000 degrees C with around 500 Watts of power. Maintaining this temperature for long periods without oxidation of wiring is also important. Furthermore, this design needs to be durable and operational for multiple trials. An additional goal is to set this furnace up with a PID (Proportional Integral Derivative) controller to control the maximum heat of the furnace.

1. Major components

The tube of the furnace is a 2” diameter quartz class tube with 5mm thickness, wrapped in about 3 layers of ceramic wool and held together with metal zip ties. Wrapped around the glass tube is 24g double twisted kanthal wiring, held in place with refractory cement. Surrounding this is a tube of sheet metal held by sheet metal screws and two metal end caps with holes cut through to allow access to the tube and for the wiring to stick out. A stand and handle made out of sewer pipe brackets is included in the design, and attached to the stand is a bracket with a plastic wiring box to act as a space to attach the PID controller, PID relay, and fuse reset. The kanthal wiring that extends beyond the tube is folded in half lengthwise (thickness of 4 24g kanthal wires) and covered in a ceramic weave tube for insulation. The wiring used for the PID and associated devices are recycled wires from an old chandelier, coated in a rubber insulation. Heat resistant tape is used to protect the wires in places where needed. A thermocouple is attached to the PID controller and inserted in the furnace. The furnace is wired to an extension cord and plugged into a programmable circuit breaker to protect the main power grid.

1. Materials

Sheet metal, kanthal wire, refractory cement, ceramic wool, quartz glass tube, nuts and bolts, sewer pipe brackets, ceramic weave wire insulation, motor control, thermocouple, heat resistant tape, voltmeter, programmable circuit breaker, handle, PID controller, PID relay, plastic circuit box, metal bracket, rivets, metal zip ties, fuse reset, metal end caps

1. Construction

1. Coat mid section of glass tube in refractory cement, score lines to allow for shrinkage during curing, let cure for several hours

2. Measure kanthal wire using the desired number of loops around the tube, with some extra length, then double the total length. Fold in half and twist the entire wire tightly using a power drill and tension. Carefully wrap wire around the cemented area of the tube, holding firmly. Hold with rubber bands and cement on top, let cure.

3. Wrap tube with wire in 3 layers of ceramic wool. Bend the twisted kanthal wiring in half to increase resistance and extend to fit where the hole sites in the casing would be. Use ceramic weave insulation and heat resistance tape. to prevent contact between wiring and the casing.

4. Bend sheet metal into a tube and secure together with screws or rivets. Drill holes to allow for wiring to come through the casing. Drill 2” holes through the end caps and secure to the tube furnace with sheet metal screws.

5. Screw on stand, add bracket with holes to the stand and screw the plastic circuit box to the bracket. Pull insulated kanthal wires into the box and wire PID controller, relay, fuse reset, and thermocouple.

5. Testing and performance

• Hit the energy and temperature requirements

• Still functional after may test runs

• Failings with the PID controller, requires the use of the motor control to control the current and prevent the furnace wires from overheating, additionally requires the use of a lightbulb to kickstart the motor control into drawing power and heating using the PID is inconsistent due to the jumps in current.

6. Things to improve on

• Need to figure out circuit configuration to power furnace without use of light bulb

• Need to figure out how to control current without motor control (for simplicity)

• Design can always be more energy efficient

TO DOs:

1. Finalize PPT for tuesday

2. Help Advaith move the pump mechanisms into the overall assembly, as well as implementing other components(Im not sure how the spin coater is going to look like)

Table 1. Inverter Truthtable

Working Folder in Google Drive: https://drive.google.com/drive/folders/1bnJyeBcbssFuE7fQBo4J-6Roz3mHzRwJ

Procedure

1. Plug in the Spin coater and the vacuum pump (if either is not able to power on try hitting “reset” on the outlet)

2. Use the arrows on the touch screen to set the spin time and rpm

3. Use tweezers to place wafer onto the o-ring so that the chip completely covers the o-ring and will seal onto it

   1. Also attempt to center the chip on the o-ring as best you can. This will minimize the chances of it flying off.

4. Use a pipette to apply liquid on top of the wafer while it is seated in the spin coater. You only need a couple drops in the pipette, don't suck up extra.

5. Close the HMDS/photoresist/SOG lid.

6. Close the spin coater lid

7. SWITCH ON THE VACUUM PUMP!

8. Press “begin”

   1. This will begin a pre spin at 600 rpm

9. Press “coat”

10. When the spin time has been reached, the coater will automatically ramp down to rest

11. Open the lid and remove the wafer with tweezers

Side Notes

If you hear the spin coater constantly beeping, this is normal. It does this because we are using a drone motor ESC, so it is programmed to make a noise after being at rest for a few minutes. It’s trying to help you find it 🙂

Feel free to turn it off using the switch in the front so the noise goes away.

Ceramic coating on both furnaces was disintegrating where wires had contact

Ceramic beads seem a little burnt but otherwise intact, Furnace 5 and 6 each had one ceramic wire still in contact with kanthal, being held together with bead despite being fried → possible only the thermocouple wire side was completely fried through, however it’s clear that both wires are under severe heat stress during operation

7/15 - Discovered kanthal wire coil on furnace 6 had been burned and rusted through

To combat this, next tube was made with as few kinks in wiring as possible, and the kanthal wire is used as the connector to the motor control as opposed to ceramic coated copper

8/25 - Since switching wiring to full kanthal and using one solid piece of wire, shorts have been discovered in the machines after repeated use. Found out the cause was due to the weave casing of wiring was being shredded through

9/8 - Incorporating the PID controller with a lack of motor control results in too much current being drawn and the kanthal wires becoming so hot they burn through the insulation weave

9/9 - Incorporated motor control into PID wiring to control current, but creates a problem where current is not being drawn unless an additional element, such as a lightbulb, is incorporated to trick the system into powering on

Best Practices

See this video for reference

1. Open this central chip count sheet, claim the next available chip number, open the blank chip view sheet for that specific chip number and record all subsequent process data into it.

2. Use a diamond tipped scribe

3. Lay the wafer on a hard, steady surface

   1. If the surface has some give, it will act as a spring when pressure is applied from the scribe

4. At an oblique angle, place the scribe tip at the edge of the flat side of the wafer

   1. Flat edge marks crystal orientation, cleaving should be easier along certain crystallographic directions.

5. Push down, don't think too hard, cleave.

   1. It may also help to press down and drag the scribe tip 1 mm outwards to the edge of the wafer.

6. Don’t move chip around with the diamond scribe to avoid scratches

   1. Use to move once a cut is made

For next week, I plan on initially CADing the base design of the spin coater(while taking into account the liquid handling + thermal heating) , and attempting to help Adwoa move her Fusion360 file of the perstaltic pump to onshape(while maintaining her sketches).

By next week, I plan on begin prototyping the pump, as well as beginning to help Advaith with full assembly of the multipurpose spin coater(since we currently are not 100% sure on whether to move the spin coater itself, or the liquid handling and heating system).

Roadblocks/issues:

• The cable that needs to be used is micro usb, and there are no cables that I could find that directly connect onto my labtop(only has C cable connections, not sure if there is a micro usb -> usb c cable)

• The stepper motor requires a different voltage from the microcontroller, so either a second power supply is needed for the microcontroller, or a voltage de-regulator(12v to 5v) is required in the electronics setup

TO DOs:

• Once syringe arrives, take measurements of it, before modifying 3d printed parts in previous cad according to those measurements, and begin testing

• Finding the right syringe for liquid handling, since the main issue was finding a syringe with the right specifications. We needed our syringe to be made out of PTFE or glass, but a majority of the ones we found were made of polyethylene, which would eventually wear out due to acetone and IPA.

• The measurements for the nozzle of the syringe that we ordered was flawed(2mm is not equivalent to 0.4 inches), so we had to take into account the chance that the nozzle isn't the same measurement as advertised

• The nozzle of the syringe was also not meant for locking syringes(but were still ordered in case we would switch back to plastic syringes), so we would have to potentially find a way to attach a needle onto the tubing from the syringe

TO DOs:

• Debug the lead screw stepper motor we have to calibrate the amount of liquid would needed to coat/clean a chip

1. This requires you to blow dry the back of the chip as well. Surface tension tends to pull the liquid towards the back

A 400C hotplate is barely warm on the edges

The main components of this project are the sensor head, oscillator, and sensing software. As of now, a prototype of the sensor head has been fabricated and tested outside of the chamber using an existing oscillator and software. Even though the sensor has not yet been tested in the vacuum chamber, all materials are ultra high vacuum compatible. In the future, the goal is that the oscillator and software will also be built and the sensor head will not be reliant on existing systems.

Concept Diagram

The oscillating signal travels from the coaxial cable through the SMA connector pin and the wire to the electrode. The aluminum base and lid serve as the ground. The signal returns through the casing. The target material adheres to the surface of the exposed quartz crystal disc causing a change in frequency of the signal.

CAD Renderings

Note: The CAD rendering does not include the wire that connects the SMA connector pin to the electrode. See Concept Diagram for an example.

Sensor Head Bill of Materials

Note: Not all materials listed are an exact match for those used in Version 1. Some materials were already available in the lab. Additionally, some of the materials used were not vacuum compatible due to zinc coatings so those materials have been substituted for vacuum compatible alternatives in the bill of materials.

Future Work

• Design a Version 2 that eliminates the need for expensive silver epoxy.

• Complete more sensor head testing.

• Build the oscillator.

• Write the code to sense the change in frequency and calculate the change in thickness.

• Create a low-cost flange feedthrough into the chamber.

Image Gallery

Documentation Document

https://docs.google.com/document/d/15uXQ0jKiw-uUwXZg3vHdAT-oS-NZu3LUEBUPLZNrHng/edit?usp=sharing

Contact

Hannah Chinn

Email: [email protected]

• Probe station setup

  • Probe station - Karl Suss PM5

  • At least 4 probes, manipulators, and coaxial to split jumper wires with hooks at the end

• Microscope setup

  • Camera - AmScope MU1000-HS and AmScope viewing software

  • Light – MI-150 Fiber Optic Illuminator

• Semiconductor analyzer system

  • 2 Analog Discovery 3s

  • Laptop with ability to connect to camera and analog discovery 3s as well as run a python program

Materials

• Devices under test – typically a finished chip with pads for probing

• Computer running AmScope viewer software and Python program

Procedure

Setup

1. Place the chip in the center of the stage and turn on the vacuum.

2. Turn on the microscope light, which appears as a spot of light on the stage.

3. Connect the microscope camera to your computer and select the camera MU-1000HS on the AmScope viewer software, which should summon the camera view.

4. Open the analyzing software on a laptop

5. Raise the stage using the lever. Focus the stage and center the pattern of interest under the light source using the knobs below the stage.

6. If the probe tips are not illuminated by the microscope light, carefully move the magnetically-attached manipulators such that the range of motion of the probe tips is within the spot of light.

7. Using the knobs on each probe’s manipulator, lower the probes so that the tips are focused yet not touching the chip, then position the probe tips above their corresponding probing pads.

8. Carefully lower the probe tips to touch the pads, which is generally indicated by resistance to movement when attempting to lower the tip further. The manual nature of this process means that the sharp probes can scratch the chip and damage the device beyond future usage, such as scratching the pads off.

9. Using coaxial cables connected to the jumper wires with hooks, connect each probe to the ground, source, and drain on the Keithley and connect the corresponding red hooks to the equivalent ground, source, and drain pins on the circuit board as well as all the black hooks to the drain pin on the circuit board like in the below picture

Run Program

1. Run the command python3 smu.py in terminal to run the program

2. This will open up a new window with a plot of the IV Curve that looks something the below picture under MOSFET I-V Curve

3. In order to close this window and continue with the program, either hit the red exit button on the image window or go to terminal and type Ctrl-C

4. If the graph had errors, repeat the experiment as necessary

5. If the data looks good, enter the title for the current and image csv files

Cleanup

1. Remove the probes from the chip and continue to the next device, either by lifting the probes or lowering the stage.

2. Raise the probes using the manipulator knobs.

3. Lower the stage by turning the lever.

4. Disconnect the microscope from your computer and turn off the microscope light.

5. Turn off the vacuum and remove the chip.

MOSFET I-V Curve

The outputs currently look something like this:

The I-V relationship between the two probes and resistance estimated from Ohm’s law should be plotted. An ideal resistor should have a linear relationship and constant resistance.

• Spectrometer

• Spectrogryph opened on computer connected to microscope view

• Calibration Graphs (should end with .sgd, can only be opened in the Spectrogryph app)

Picture of Spectrometer Below:

Materials

• Silicon Chip with 700B/P5O4 SOG

Steps

Setting up the software + obtaining spectrometer data

First, ensure that the spectrometer is connected to the computer.

In addition, place SoG on silicon chip sample on the slide under the microscope.

1. Open Spectrogryph software on Computer

2. Under Plot/Views, select “New Acquisition View”

After which, you should see something that looks like:

1. In the upper left corner, select “Device Type” and select ASEQ. Then press connect.

2. Change exposure to 5000 ms (or more, if you want less noisy data)

3. Select single shot or continuous

   1. Use Single Shot if you want to get one graph that is taken after 5 seconds of exposure

   2. Use Continuous if you want a graph that is constantly being recorded (hence changing)

4. Pressing “Acquire” would start the readings. Before pressing “Acquire”, ensure that the probe is connected to the microscope (will need to press the probe against the microscope to get good readings, as shown in picture below).

7. Once a graph of Count against Wavelength is obtained, we need to normalise the counts. This is done by clicking on "Process" and "Normalise (Peak)".

1. Once normalized, we can now save this spectral plot in file (save it in the .sgd format, so that you can re-open it in spectrogryph later)

Determining Thickness of SoG

1. Create another New Acquisition View

2. Drag the Calibration graphs file (should end with .sgd) into the New Acquisition View

You should see this:

The color of the graphs correspond to the actual observed colors of the glass. This can serve as a good benchmark as to what the thickness of your glass might be.

As seen, the SoG with the lowest thickness (190 nm) had the maximum peak at a wavelength of ~590nm. As the glass thickness increases from 190 nm to 255 nm, the wavelength at maximum peak increased accordingly. Following that, from 255 nm to 276 nm, it can be seen that a second peak is starting to form (at a wavelength of around 480 nm). Finally, from 276 nm to 314 nm, the peak at 590 nm disappears, and now the peak at 480 nm becomes more distinct.

1. Lastly, drag the .sgd file that you previously saved in Step 7 into the plot above.

2. Determine which shape your graph most closely resembles to determine SoG thickness.

Also note that the color of your glass is a pretty good indicator of what thickness it will be. So for instance, if your chip looks pink, just by looking at the calibration graphs, we can determine that thickness is around 270 nm.

Useful Links

• Spectrogryph Manual Website: https://www.effemm2.de/spectragryph/about_help_manual.html

Semiconductor Parameter Analyzer

Not all transistors are created equal. There is an immense amount of information within the electrical characteristics of the device that helps with optimizing the manufacturing process (Read Peter Van Zant Chapter 14). Below is an example of an ideal IV curve from a textbook, and the first IV curves taken in the Hacker Fab. While our curves aren’t perfect, they do exhibit transistor-like-characteristics 🙂.

IV curves are not the only tests that can be done with a parameter analyzer. With enough data, trends in these different curves can be directly associated with process parameters.

Probe stations are traditionally heavy desktop machines that hold probe manipulators. The purpose of the probe station itself is to precisely move the tungsten probe in order to make contact with the contacts of the device. This typically means moving 3 individual probes to the gate, source, and drain contacts, and another to contact bulk.

Probe Station + simple diagram of contact locations

These probes are attached to the back of the Semiconductor Parameter Analyzer - precision instruments consisting of multiple SMUs (Source Measure Units) and a built-in computer to control them and store readings. Source Measure Units are glorified power supplies with built-in voltmeters and ammeters - they are very precise instruments that are able to supply voltage or current through the probes, and simultaneously read voltage or current.

Open the lid.

We are building a low cost Atomic Layer Deposition machine for the Hacker Fab to achieve improved gate dielectrics, which will help us achieve our goal of a 10 micron CMOS process as well as improve our capability in performing thin-film research. Our design work on it will be all open source, and we hope other labs can use our work to make their own ALDs at a fraction of the cost of commercial alternatives. We are building our ALD to fit 4" wafers so that it can be brought into the nanofab, which will help us lower the barrier to entry for researching thin film deposition and new materials. Although 4" is much larger than anything we are currently using in the Hacker Fab at CMU, this larger size will make it useful to a larger audience.

Our work thus far has been focused on machine design, largely drawing from two papers on “DIY” ALD machines: “Design Of Atomic Layer Deposition Reactors For The Deposition Of Nanoparticle Embedded Thin Films” by Michael Lubitz, and “Homebuilt Reactor Design and Atomic Layer Deposition of Metal Oxide Thin Films” by Pamburayi Mpofu. Each of these papers describes their machine design followed by some process development where they describe the settings (ie. temperatures and precursors deposition times) used in their initial depositions.

Bill of Materials

A complete list of parts and components used in making the DIY ALD system can be found here.

Precursor Selection

Oxide of interest

For the current system we aim to deposit Indium-Tin Oxide. Indium Tin Oxide (ITO) is a versatile material widely recognized for its excellent electrical conductivity and optical transparency. These properties make ITO a promising candidate for advanced applications, particularly as a channel material in thin-film transistors (TFTs). Its high carrier mobility and tunable electrical characteristics offer significant potential for improving TFT performance in display technologies and flexible electronics. Additionally, ITO thin films are of great interest in materials and thin-film research due to their unique combination of metallic and semiconducting properties. This makes them an ideal system for exploring novel deposition techniques, optimizing film uniformity, and investigating structure-property relationships.

The precursors for the metals were chosen based on their feasibility to react with water vapor as the oxidizer. The precursors chosen are Trimethyl Indium (TMIn) for Indium and Tetrakis(dimethylamino) Tin (TDMASn) for Tin with Nitrogen carrier gas. They have been shown to be used for ALD and CVD processes with water as the oxidizer in literature. As a starting point our aim would be to reproduce the results achieved in [Zhang et al.]. The process parameters highlighted in the paper are as follows (substrate temperature: -225C):

For the first attempts at deposition however, the research group at CMU will attempt to deposition Al2O3, as this process is well-documented in the CMU Nanofab. Then, the group will attempt to deposit more complex oxides such as ITO.

Safety Considerations

Most precursors and specifically metal organic precursors used for CVD and ALD processes tend to be pyrophoric (i.e. thermally unstable and spontaneously ignite on exposure to air) thus necessitating safety measures.

Material Considerations

Compatibility with the precursors and byproducts produced during reaction are important to consider when selecting components for the delivery system. For our given precursors the chemical groups for which we checked compatibility are: 1) ability to handle pyrophoric materials, 2) ability to resist corrosion due to water vapor, 3) compatibility with methane (by product of TMIn reaction with water) and dimethylamine gas (by product of TDMASn reaction with water)

The compatibility of o-ring materials was checked on the following sources: (1) (2)

Specific choices:

• Stainless Steel Tubing

• Aflas O-rings - conventionally used Viton O-rings are incompatible with dimethylamine

• Aluminum vacuum chamber

• Stainless steel bellow hose

• Vacuum pump - Although the vacuum pump manufacturer warns against using the pump with pyrophoric gases, this caution can be safely disregarded in our case. Since we will be working with extremely dilute concentrations of these gases, the risk of combustion or hazardous reactions is significantly minimized. The low concentration ensures that the gases remain well within safe limits, allowing for the pump's use without compromising safety or performance.

Sourcing Precursors

Given the safety considerations involved in handling the pyrophoric precursors, the sourcing of materials for ITO deposition is managed by the Claire & John Bertucci Nanotechnology Laboratory staff. They ensure that all necessary precautions are taken during the procurement, handling, and storage of the chemicals. The required precursors have been ordered from Strem Chemicals, a trusted supplier known for providing high-quality materials for advanced research and industrial applications. TMIn, TDMASn

Key Components

ALD precursors and co-reactants are self-limiting

1. Precursor and co-reactant selection

   1. Have to be reactive with the surface groups

   2. Volatility, thermal stability, and reactivity have to be high

   3. Different ways to deliver the precursor to the chamber

2. Chemical composition

   1. Checking if the intended materials are being deposited through X-ray photoelectron spectroscopy (XPS) or four-point probe conductivity measurement

   2. Optimization of the parameters

   3. Chemical composition and stoichiometry will determine the final material properties

3. Thickness control

   1. Want to deposit the same amount of material in each cycle

   2. Thickness is determined per cycle (growth per cycle or GPC)

   3. Keep track of material increase during deposition and deposit multiple samples with a varying number of cycles (Thickness vs. ALD cycles)
4. Saturation

   1. Need to optimize precursor dosing time, precursor purging time, co-reactant dosing time, and co-reactant purging time (two-step process)

   2. Choose a relatively long time for three of the four while varying the fourth

   3. Confirm saturation when increasing the dosing or purging time does not increase or decrease the GPC any more (do with all steps of the procedure)
5. Material properties

   1. Optical properties (refractive index, absorption coefficient)

   2. Electrical properties (resistivity, carrier density, mobility)

   3. Surface morphology (roughness, crystallinity)

6. Temperature dependence

   1. ALD window where the GPC is nearly constant for reliability and repeatability despite slight change in temperature

   2. Constant GPC is not necessary but verifying saturation is important for all varied temperatures

   3. Temperature dependent GPC exist but show saturating ALD behavior over a wide temp. range
7. Uniformity

   1. Verified saturation in one area doesn’t mean dosing is sufficient everywhere

   2. Place the largest fitting substrate into the chamber and check for thickness variation as well as material properties

      1. Thickness uniformity may be good but the resistivity might vary significantly over the substrate

8. Conformality

   1. Ability to deposit on 3D structures with no variation in thickness (trenches or vias)

   2. Check for conformality

      1. Deposit a vertical trench or via with a certain aspect ration (AR = height/width)
9. Nucleation behavior

   1. Different film growth behavior from beginning to end

   2. Linear growth, accelerated growth, and delayed growth

   3. Nucleation behavior can affect material properties (defects, pinhole density, crystalline structure, and film resistivity)
10. Other important aspects

    1. Stability of the films over time and sensitivity to the environment

    2. Reproducible film thickness and properties

    3. Avoid overdosing and required precursor dosing depends on the surface area of the substrate (larger when working with 3D substrates)

References

Z. Zhang et al., "Atomically Thin Indium-Tin-Oxide Transistors Enabled by Atomic Layer Deposition," in IEEE Transactions on Electron Devices, vol. 69, no. 1, pp. 231-236, Jan. 2022, doi: 10.1109/TED.2021.3129707.

“Design Of Atomic Layer Deposition Reactors For The Deposition Of Nanoparticle Embedded Thin Films” by Michael Lubitz

"Homebuilt Reactor Design and Atomic Layer Deposition of Metal Oxide Thin Films" by Pamburayi Mpofu

• Probe station setup

  • Probe station - Karl Suss PM5

  • At least 4 probes, manipulators, and coaxial cables

• Microscope setup

  • Camera - AmScope MU1000-HS and AmScope viewing software

  • Light – MI-150 Fiber Optic Illuminator

• Keithley semiconductor analyzer system

  • Keithley 4200-SCS Semiconductor Parameter Analyzer

  • Keithley 2636a Sourcemeter

  • Keyboard and mouse

Materials

• Devices under test – typically a finished chip with pads for probing

• Computer running AmScope viewer software

• Flash drive for data transfer

Procedure

General setup and cleanup

1. Place the chip in the center of the stage and turn on the vacuum.

2. Turn on the microscope light, which appears as a spot of light on the stage.

3. Connect the microscope camera to your computer and select the camera MU-1000HS on the AmScope viewer software, which should summon the camera view. The Keithley semiconductor analyzer has only two USB ports, which are currently occupied by a keyboard and mouse. Without WiFi or a USB hub, the camera view and data transfer are handled by another computer.

4. Turn on the Keithley semiconductor parameter analyzer.

5. Open the KITE software and the experiment of interest (see below sections).

6. Using coaxial cables and connectors, connect each probe to the corresponding port on the Keithley semiconductor parameter analyzer.

7. Raise the stage using the lever. Focus the stage and center the pattern of interest under the light source using the knobs below the stage.

8. If the probe tips are not illuminated by the microscope light, carefully move the magnetically-attached manipulators such that the range of motion of the probe tips is within the spot of light.

9. Using the knobs on each probe’s manipulator, lower the probes so that the tips are focused yet not touching the chip, then position the probe tips above their corresponding probing pads.

10. Carefully lower the probe tips to touch the pads, which is generally indicated by resistance to movement when attempting to lower the tip further. The manual nature of this process means that the sharp probes can scratch the chip and damage the device beyond future usage, such as scratching the pads off.

11. Press the green triangle in the KITE software to run the experiment.

12. Once the experiment finishes, check the data for errors and repeat the experiment as necessary.

1. Scale the graph such as by right clicking the graph and clicking Autoscale and save the data in a folder named chip### where ### is the chip number. To save the graph and data with a common name, type the name and click Populate, Save All, then Exit.

2. Remove the probes from the chip and continue to the next device, either by lifting the probes or lowering the stage.

3. After all experiments are finished, transfer the data to a flash drive and upload the data (such as to Google Drive).

4. Raise the probes using the manipulator knobs.

5. Lower the stage by turning the lever.

6. Turn off the Keithley parameter analyzer.

7. Disconnect the microscope from your computer and turn off the microscope light.

8. Turn off the vacuum and remove the chip.

MOSFET I-V Curve

1. Upon opening the KITE software, choose the vds-id test from under the section 4terminal-n-fet.

2. Configure the probes and measurements using the following parameters. Make sure that the correct coaxial cable (SMU1, SMU2, GNDU) is connected to the correct probe.

1. The I-V curve of the MOSFET and the gate leakage current should be plotted. Note the magnitude of the voltage and current measurements. Very low current in the range of nano-amperes or below can indicate an open circuit, and linear behavior can indicate a short circuit, which can arise from a fault in the device or improper probe placement.

Gate & Contact Resistance

1. Upon opening the KITE software, chose the res2t test froom under the section 2-wireresistor.

2. Configure the probes and measurements using the following parameters. Make sure that the correct coaxial cable (SMU1, SMU2) is connected to the correct probe.

1. The I-V relationship between the two probes and resistance estimated from Ohm’s law should be plotted. An ideal resistor should have a linear relationship and constant resistance.

Post Spin Coating

1. Particulate/dust contaminating wafer surface.

   1. Often, after spin coating disruptions to the SOG evenness/thickness can be seen in localized spots on the wafer. There are possible causes of this…

   2. Some SOG has hardened inside the bottle creating fine flakes of SiO2. These flakes then get sucked up by the pipette and deposited onto the wafer with the liquid SOG. These flakes are clear and sometimes not visible pre spinning, and are then only visible after spinning.

2. Particulate Landed on the wafer during spinning. Sometimes the spin coater can create turbulent air and kick up dust from inside the spin coater which then lands onto the wafer.

3. The wafer had a preexisting scratch or mark big enough to cause surface tension issues which result in the liquid SOG “un-wetting” in that spot and exposing the substrate. These scratches are often caused by scratches that occur during cleaving, slipping across the wafer when using hard tip tweezers, or dropping the wafer.

1. Radial variation in thickness/diffraction color

   1. Sometimes after spin coating, there may be a radial pattern of changing color on the wafer. The varying colors indicate variation in thickness since SiO2 is translucent so thin films diffract and appear different colors based on thickness. These variations are usually on the order of a few hundred Angstroms (A) (film thickness ~2000 A) and may not warrant restarting.

During Spin Coating

1. Wafer flies off the chuck while spinning

   1. Sometimes either due to bad two sided tape adhesion (regular spin coater) or improper sealing onto the vacuum chuck (vacuum spin coater). The chip may fly off the chuck due to inertial forces. This usually warrants restarting since when the chip flies off it hits the side causing uneven spreading of the SOG or lands onto the SOG.

Post-Anneal

Identifying “defects” in the deposited SOG

Pinholes

Possible Causes

1. Scratches or dust particles on the wafer Cause the liquid SOG to “un-wett” in some spots. This essentially creates a dip in the SOG layer that extends to the wafer surface below the SOG.

Particulate resting on top of the SOG

Possible Causes:

1. Dust coming into the fume hood and landing onto the wafer after the SOG layer has solidified.

Procedure

Prepare the Transistor:

• Ensure that the transistor surface is as clean as possible to minimize probe-to-pad contact issues. It is helpful to have another user with you to properly align and contact the pads without damaging other probes or the transistor surface.

• Ensure that the transistor is properly connected and biased for C-V measurements (i.e. for an NMOS transistor, ground the bulk and source contacts, apply voltage from the gate or drain depending on the type of measurement).

Measurement Setup:

• Set up the CV measurement equipment, we use a Keithley 4200-SCS Parameter Analyzer as our test equipment and Probe Station for circuit connections. Please follow the steps given in the Probe Station Manual to ensure proper probe-to-pad contact with the transistor.

Voltage Sweep:

• If using an NMOS transistor with 3 terminals (i.e. no bulk contact), turn off the bulk probe on the KITE interface, ground the source pad, apply a small-signal AC voltage to the drain pad (constant frequency ideally above 100 Hz, low frequency measurements will be performed later), apply a large-signal DC voltage sweep to the gate pad (-8V to +8V for our case). Measure the total capacitance from the gate pad as well. If your NMOS transistor has a bulk pad as well, it is possible to modulate the bulk potential and model threshold voltage dependencies. For regular use, grounding the bulk and/or at least having it at the same potential as the source pad is ideal.

• It is also possible to model the MOSFET as a MOS capacitor instead by connecting source and drain to the ground and only by sweeping the gate voltage. This “topology” may be deemed ideal to extract capacitive parasitics from the measured total gate capacitance:

  • When in accumulation (VGS < 0), mobile holes from the p-type substrate form a dielectric region due to being attracted under the gate. The total gate capacitance is the sum of the gate-source and gate-drain overlap capacitances, along with the gate-bulk capacitance.

  • When in depletion (VGS is a small but positive voltage), some number of mobile electrons are attracted under the gate but not enough to fully invert the net channel charge, therefore the region under the gate simply becomes devoid of mobile charges, but becomes more negative as the gate voltage is increased. Total capacitance is the sum of the overlap capacitances (which are often neglected due to their small magnitude) and the oxide capacitance (between the gate oxide and the induced weak negative channel) in series with the depletion region capacitance. This parallel topology decreases the total capacitance.

  • When in inversion (VGS >> 0, much larger than the threshold voltage required to “turn on” the MOS), a substantial number of electrons are attracted under the gate such that a strong conduction channel forms. The conduction channel forms the bottom plate of this virtual capacitance, and the distance between this bottom plate and the gate decreases as the channel inversion becomes stronger (with increasing gate-source voltage), increasing the total capacitance. Apply a DC voltage sweep to the transistor, typically from negative to positive bias (usual measurement range is from -8V to +8V). Measure the capacitance at each bias voltage.

Plotting CV Curves: Plot the measured capacitance as a function of the bias voltage. Below is an example of a measured capacitance versus applied voltage (C-V) curve. Note the decrease in the total capacitance as the mode of operation changes from accumulation in the deep negative voltages to depletion as the capacitance decreases significantly. There is no bulk contact in this measured NMOS transistor, and therefore the inherent and uncontrollable modulation in the bulk potential may be preventing the change of the mode of operation from depletion to inversion (note the lack of increase in the capacitance as the gate potential approaches +8V).

Analyzing C-V Curves: The shape of the CV curve will provide information about the doping concentration in the silicon substrate.

• Dopant Concentration (ND): To measure the concentration of the deposited donor atoms, either the source or the drain terminal of the NMOS is used with respect to the bulk. If the drain and the gate are grounded, the subsequent capacitance measurements will be done between the bulk and the source terminals. Since the source and the bulk regions are oppositely doped, they form a p-n junction with a depletion region in between. This structure presents inherent diode and capacitive properties, which is ideal for doping concentration and profile measurements. The average doping should be extracted to later calculate the Debye length (in plasma physics, the distance at which a charge (among a sea of other charges) is shielded against electrostatic forces of a charged plane, such as that of a capacitor), flat band capacitance and bulk potential.

• Flatband Voltage: Flat band voltage is the voltage that must be applied to the gate terminal at which the metal-oxide-semiconductor interface potential becomes equal in magnitude to the built-in potential, making the surface potential zero. Since the presence of a flat band condition affects the accumulation of charges for accumulation or inversion channel formation, it is an important parameter to extract for the modeling of the threshold voltage. VFB is usually interpolated from the C-VGS curves, if and only if the doping profile is assumed to be uniform over the region and interface trap state density is large. Otherwise, measuring the flat band voltage is finicky at best and extremely difficult at worst due to our fabrication methods.

• Metal-Semiconductor Work Function Difference: The work function difference is a key parameter in determining the threshold voltage of the MOS transistor since the WMS forms a potential barrier against the inversion of the channel. The bulk potential, which is extracted using the doping profile, is an input to WMS.

Model Fitting: As a general rule of thumb, for long-channel devices such as ours, 1 MHz is the frequency at which high-frequency measurements are performed, while low-frequency measurements are generally performed at and below 100 kHz, down to 1-10 Hz.

Use semiconductor device simulation software or a theoretical model to fit the experimental CV curve to theoretical curves, which depend on the doping concentration. This can provide a more accurate estimation of the doping concentration. See the ideal CV curve below:

Extract Parameters: From the fitting or analysis, extract parameters such as doping concentration, and threshold voltage using known parameters such as oxide thickness. See page 10 of this document for a detailed explanation of the relevant equations. This file has an implementation of those equations in MATLAB.

Future Work

As of June 2024, we are currently working on our own custom probe station and source-measurement unit, as described here. Once this is complete, we will be able to use our new setup to take CV measurements. We will update this page accordingly once this is done.

Reference Sources

• C-V Testing for Components and Semiconductor Devices

• Making Optimal Capacitance and AC Impedance Measurements with the 4200A-SCS Parameter Analyzer

Littrow ECDL

The coherence length of an inexpensive diode laser is around 1mm which is insufficient for the range of motion of the stepper (~2cm). To increase this length for usable interferometry, the source for the interferometer will be an external cavity diode laser (ECDL) instead of just the diode. This is achieved by shining the laser onto a diffraction grating, where the wavelength is chosen by spatially filtering the angle of the reflected light using a pinhole. For simplicity and reducing points of failure, the laser is not tunable, which is one of the main disadvantages of the Littrow configuration.

Optical Isolation

For optical isolation of the interferometer output and the ECDL output, we use polarizers and 90 degree wave rotators (already an inexpensive alternative to half wave plates for rotating the polarization), which is inexpensive compared the setup using a quarter wave plates and polarizing beam splitters by over a thousand dollars. This setup prevents feedback of the mixed light back to the ECDL, and isolates the interferometer output at the detector.

Transimpedance Amplifier & Software Filtering

The small quantity of light is too small to produce a photodiode current, when connected to a resistor, that registers on an Arduino (0-5v), so we boost the dynamic range of the signal using an op amp connected in the simple transimpedance amplifier setup. Because the laser is being operated at low power for short time periods (<100ms) we do not implement precise temperature control. We use Arduino Nano for measurement and control.

Bill of Materials

Total: $640

Purpose