James Lin

ALD Project Proposal: https://docs.google.com/document/d/1hN6o0-Mjtj6w6XVKbcjDsQGZm-uqVoWmuRubTbs2fYQ/edit?usp=drive_link

Packaging Project Proposal: https://docs.google.com/document/d/1mPezRVWu7PNa3ggTOlxjDEdb9D6B84CEXgIU-5ACNHs/edit?usp=drive_link

Weekly Update #13

ALD:

Progress:

• all exhaust fittings arrived except for 1" tubing

• sent email to Matt asking about water ampule and exhaust installation

• added grommets to delivery storage

Challenges:

• we tried to fill water ampule, did not succeed, opening was too small and air inside prevented water from flowing in

• we are very tight on time to get the system to deposit before school ends, major hold up being the exhaust

Plans:

• install exhaust

• fill water ampule

• work on final presentation and documentation

Packaging:

Progress:

• Soldered all components for two packages and motherboard!!!!

  • was able to test fit everything successfully

Challenges:

• will be a bit short on time to do wire bonds and testing before final presentation

Plans:

• wire bond on Tuesday

• IV curves before final presentation?

• work on final presentation and documentation

Weekly Update #12

ALD:

Progress:

• Ordered tubing and KF connections for exhaust

  • KF40 hose will hook from delivery storage straight up

  • KF25 etcher and ALD vacuum will hook individually to either side of lab room

  • need to also wait for Matt to give us the exhaust connections

• Ordered grommets to facility negative pressure inside of delivery storage, they come without hole so we can cut them to whatever size we want or keep as plug

• Designed 3d printed covers for non circular holes as well, they have been installed

  • printed out of ABS and should withstand heat tape temps

Challenges:

• exhaust connections will not be likely to come before demo due to delivery times

• mane

Plans:

• work on exhaust when parts arrive

• erm Viswesh when do we wanna try filling the DI water into the ampule for our first pulse test

• work on poster

Packaging:

Progress:

• waiting on PCBs, digikey and mcmaster parts arrived

• printed encapsulation cap - used ABS

• finished packaging BOM: https://docs.google.com/spreadsheets/d/1h7u_Eif3jr8CX-VDs7G6TskFq9B_RoVnjoTQv3pn7rc/edit?gid=0#gid=0

Challenges:

• Likely won't be able to show package by demo time due to PCB delivery, but if come early next week we will have something to show at least if i grind super hard

• wire bonding success is still a big uncertainty, but cant test until we have board and chip

Plans:

• wait for PCB to arrive, if here early enough will need to bust my ass to solder and reflow everything before thursday

• work on poster

Weekly Update #11

ALD:

Progress:

• got the push to connect for valve gas and its connected to lab supply!

Challenges:

• nothing so far, just tight ish timeline for the rest of integration until end of sem

Plans:

• meet with Viswesh and Matt in the coming week to plan out exhaust for ALD

• buy exhaust tubing

• work out kinks with heating tape once test happens

Packaging

Progress:

• Altium for both resistor chip and motherboard done and will be ordered on Monday!!!

• McMaster and Digikey parts on purchase tracker

• Talked to Joel a bit about packaging for next sem and had a few areas of interest:

  • Wafer cleaving solution:

    • currently chip is very big and we dont have guarantees that we can cleave them very accurately by hand

    • this increases parasitic resistance by making the bonding wires a lot longer than they should be

    • Making a cleaving jig with small diamond disk attached to a high speed motor?

    • Plasma etching to cut dies?

  • Look into flip chip on board via reflow:

    • would need updates on nickel plating and verification that we can grow tall aluminum pads

    • we also have not verified that our chips can withstand reflow temps

  • look into chip in package:

    • if we can cleave chips accurately, then a we can size for chip in package with more certainty

    • another possibility is copper/nickel plating onto 3D printed resin parts, which may be a solution to the lead frame problem

• Brief summary of boards:

  • The packaging solution we have uses a chip on board approach and is separated in 2 parts:

    1. the actually package that has the chip in the center of the board and uses aluminum wire bonding to connect IO pads to the PCB

    2. a motherboard with 2 package slots that has IO for the Anolog Disovery 3 (https://digilent.com/shop/analog-discovery-3/) we will be using for electrical characterization tests

    The current resistor chip package is just 8 rows of doped Si resistors with varied widths to help us test for overall contact and parasitic resistances of our wire bonding connections. Each pin has a 0.1 uF decoupling capacitor as well The motherboard has a pull up or pull down resistor slot for each pin in the case that we will be doing toggling for logic circuits in the future, and I've also added decaps near the output pins

• Board PDFs:

Challenges:

• boards took a longer than anticipated to do partially due to school work and partially due to wrestling with Altium

• Had to keep pin labeling super vague since we expect to be putting different packages on this

Plans:

• look into resin printing material and see if we can minimize the package cap melting if we need to put soldering iron near package to make modifications to passives

• print package cap

• maybe make a platform out of PLA to hold motherboard

• wait for board and parts to arrive

• add to metrology project description for next sem

Weekly Update #10

ALD:

Progress:

• wrapped 4ft heating tape around the manifold line and verified that 2ft heating tape works for our ampules

  • turns out we ordered the wrong quantities for the two heating tape lengths lol

  • new heating tape has been ordered

• cylinder is fixed/replaced, carrier gas supply is fully integrated with system

• Viswesh tested vacuum of the whole line, after some time with vacuum on, we were able to reach 3 mTorr/min of loss, which was decided to be acceptable during actual use

Challenges:

• we never found the last push to connect fitting to integrate N2 gas for ALD valves, had to order that as well

• the heating tape and push to connect may not be ready by demo 2

Plans:

• secure heating tape more tightly

• finish valves gas supply and troubleshoot

• presentation 2

Packaging:

Progress:

• footprint for our 16 pin chip is created in altium!

  • specs:

    • pink sq is the maximum allowed chip size (14mm x 14mm)

    • yellow sq is the theoretical chip size (10mm x 10mm)

    • each pad is 1.5mm x 0.5mm with 0.5mm gap between each other

      (reccomended pad width and spacing is ~0.38mm but i wanted to be safe)

    • the two rows of pads are set to leave a 2mm gap to the pink sq

• schematics are also mostly done

  • need to add pull down resistor slots and decoupling capacitor slots and need help with understanding what best fits our chip testing application

    • Pull up/down resistors: https://eepower.com/resistor-guide/resistor-applications/pull-up-resistor-pull-down-resistor/#

    • Decaps: https://resources.altium.com/p/what-size-decoupling-capacitor-should-i-use-my-digital-ics

• our pads will need to be ENIG plated

  • explanation of the plating here: https://pcbtrace.com/enig-plating/#:~:text=For%20Chip%20on%20Board%20(COB)%20assembly%2C%20manufacturers,protecting%20layer%20preventing%20the%20Nickel%20from%20oxidizing.

  • unsure how gold is conducive to a good electrical bond for AL wires, will need to look more

• Also took pictures of wire bonds on my resistor lab chip

  • was not able to make a fully successful bond, pads were too weak, and short bond distance lead to breaking at the joint

Challenges:

• Carnival week meant not as much work was done was planned :<

• lead time for PCBs might be too long 😭

• wire bonding will be very finicky to do

Plans:

• LOCK IN on Altium and get a workable file sent out as soon a possible

• figure out how to specify ENIG finish to digikey

• presentation 2

Weekly Update #9

ALD:

Progress:

• H2O ampule delivered from Swagelok!

• The line is connected to both the chamber and the N2 cylinder

• Final steps for ALD valve gas is still waiting on McMaster push to connect fitting

• Viswesh did vacuum test with line connected today, we can reach 20 mTorr pressure but loses at 3 mTorr per minute

Challenges:

• Identifying leaks in the line will probably not be trivial

Plans:

• Will be working with Viswesh for vacuum stuff

• Look for/reorder push to connect to finish up the ALD valve gas line

Packaging

Progress:

• We were able to talk to Jim Bain after during his guest lecture:

  • He basically gave approval of the chip on board concept for this semester, he also came to the conclusion that chip in package would be too finicky and hard to replicate for other people

  • He strongly suggested that we just order the boards for packaging as opposed to making it ourselves, mainly due to wire bonding needing a specific coating on PCB pads to work reliably (prob something like this that Icey sent but need it for aluminum specfically: https://www.protoexpress.com/kb/enig/)

  • he also seems fairly confident about our IO pads just being 3um thick AL pads, since AL is fairly reactive and prone to form oxides (good for adhesion) and its ductility will help prevent pad cracking and the wire from pushing beneath the pad

• Made some progress with Altium schematics, got the connectors and netlists figured out

  • need to figure out how to make the custom footprint for the wire bond pads

• Also did a wire bonding test with my group's resistor lab chip, will get microscope pics in a few days but here are some main takeaways :

  • The 0.48 um aluminum pads are way too small and lifts up fairly easily (though I was able to make first bond with one of them)

  • the wire pulling is very scuffed, and the bonder can only pull in one direction

    • we probably wont have problems with this, but the joint will snap super easily if ur wire bond is too short

    • the wire in general snaps super easily at the joint if the wire is dragged off axis during the bond

  • if the pad comes off during bond, clogging the machine is likely, which may be painful to fix

  • also took a pic of some recommendations for bonding surfaces in the lab

Challenges:

• Thermal fluids experimentation continues to make me hate my life, but there will be less deadlines for me leading up to carnival, so I am really hoping to be more productive with packaging work for this coming week

Plans:

• take microscope pics of the resistor lab chip wire bond test

• finish out the Altium schematics and layout to hopefully get some feedback by end of week

• figure out the specific PCB pad finish that will be compatible with AL wire bonding

Weekly Update #8

ALD:

Progress:

• Mid sem documentation finally done last week

• ALD valve gas line sucessfully integrated into the lab, and we get sufficient pressure without leaks!

• Yippie delivery storage mostly assembled

  • modifications on the floor made - 3 new holes were made

  • retaining plates waterjetted - manifold is well secured now

• Two stage regulator installed with Viswesh, need help with opening the cylinder to verify it actually works 😭

• Still waiting on empty cylinder but confirmed with Zach that they have started manufacturing

Challenges:

• Matt wasn't able to get us the tube bender before the conference, but shouldn't be a big deal for us

• I anticipate that we will run into the most issues with routing tubing to the regulator and with wrapping the heating tape going forward

• otherwise progress for delivery storage is in a pretty good place

Plans:

• get tube bender and figure out how we will connect cylinder to MFC to manifold

• work on presentation two

• talk to Matt to move along plan with exhaust for overall ALD system (storage and vacuum)

• not much else due to lead time on ampules

Packaging:

Progress:

• Again not much :(

• Finished mid sem documentation as well last week

• Heard from Joel that Jim Bain has some ideas for packaging

Challenges:

• been swamped with school work, but will be able to put more time into packaging now that a good chunk of physical work for ALD is finished

Plans:

• Get Altium chip on board package design to a good place this week

• Dig into literature on wire bonding and start organizing research

  • Need to create list of failure modes to look out for

  • Create a much better supported justification for our wire bonding decisions

• Talk to Matt and Joel on Tuesday about packaging ideas

Weekly Update #7:

ALD:

Progress:

• Empty cylinder for H2O finally ordered today after the long saga

  • The cylinder assembly ended up being ~1.75in longer than CAD, so we are going with the hole underneath the water ampule

  • We were also able confirm SC-11 cleaning for the cylinder, but this is not promised as welding cannot be done in clean room

  • The final price also increased to $483.52 and will arrive in 1-3 weeks

• Sheet metal parts arrived!

  • The parts seem to fit well with each other

• Everything seems to fit

• otherwise not much

Struggles:

• Documentation is late, had less time over break than anticipated from family matters

• Need try squeezing out time for fabrication and assembly work

• Relatively long lead time for the empty ampule may put a wrench in testing the overall ALD system

Plans:

• Finish documentation ASAP

• Waterjet retainer plates in TechSpark or elsewhere

• Cut hole in storage floor for water ampule

• Storage assembly and test for interference

• Work on integrating the N2 gas line for the ALD valves

Packaging:

Progress:

• Unfortunately I was not able to get a lot done over break :(

Struggles:

• Same deal as ALD, documentation is behind, but since ALD is my main project I will be prioritizing that first

• A lot of work for ALD will be done this week, but will try to make as much progress on Altium design as I can this week

Plans:

• Also documentation ASAP after ALD one is done

• Altium Altium Altium, preferably in a good place by end of week

• Get some spare time to compile some wire bonding failure modes that we should be looking out for and include in documentation

Weekly Update #6:

ALD:

Progress:

• Some more orders for valves gas line assembly

• got quote from Swagelok that offers cylinder assembly for half of STREMS price

  • $800 -> $400 yay

  • assembly is 2.6" too long and unsure if the cleaning standard matches

  • sent email back to check if can shorten by 1"

• Also made retaining plates for clamping down manifold

Struggles:

• Possible problem with waterjets, but can use CMR waterjet as a backup if techspark is still not up

• Possible inconvenient design changes may be needed due to the water ampule being too long

  • we either move manifold up: requiring making two holes bigger, redesigning chamber tube, and cutting extrusions shorter

  • or we cut a hole under the water ampule

Plans:

• Continue to communicate with Zach from Swagelok and figure out the plans for water ampule

• Waterjet the retainer plates when come back to school

• Documentation

Packaging:

Progress:

• Learned a lot from Prof. Radway's packaging guest lecture

• Found some documents talking about IO pad design:

  • https://www.we-online.com/files/pdf1/design-rules-wire-bonding-cbt-en.pdf

  • https://nrf.aux.eng.ufl.edu/_files/documents/3201.pdf

  • https://www.edaboard.com/threads/information-about-designing-io-pads.186647/

• Meeting with Icey to discuss plans for IO pads

  • Plan to use first resistor testing chip as a trial to identity possible failure modes for wire bonding

  • We will do regular aluminum IO pads and see how well it works

  • Did some math to figure out that chip cannot exceed 14mm x 14mm for wire bond clearance

• Joel and I also found out that the MEMS lab PCB mill doesn't work, but we can try to use the one that has been sitting in Techspark for a long time

Struggles:

• there are lots of uncertainties about how our wire bonds and IO pads will perform, so will need to have a well researched set of failure modes to look out for

Plans:

• do more research on IO pads and wire bonding failures

• aim to have PCBs designed by Monday 3/10

• PCB mill the week of school starting

• Wire bonding around 1.5 weeks after school starts again

• Documentation

Weekly Update #5:

ALD:

Progress:

• Delivery storage design finalized

• All delivery system fittings are ordered

• All hardware in tracking sheet, unfortunately sheetmetal wont be here by start of spring break

Plans:

• get retaining plate for U bolts designed in CAD, planning on water jetting the 0.1" AL left over from substrate heater right after spring break, aim to have design finished by end of week

• need to also order LED strips for delivery storage

• also need to get the empty ampule ordered 😭

Struggles:

• school work is keeping me really busy and I'm pretty exhausted in general

• should've gotten the orders in sooner, but given that sheetmetal won't arrive on time, we should be ok

Packaging

Progress:

• Finally decided on doing chip on board packaging

• I have a finally made a design concept for the packaging in CAD

Plans:

• find time to make the Altium design for package

• To Joel: is Thursday ok to do PCB mill?

• work on getting the mother board and encapsulation ready over spring break

Struggles:

• school work is pretty bad this week, not sure how much time I can put into this but will try

Weekly Update #4:

ALD:

Progress:

• Grinded out design for delivery storage, some major design elements and specs:

  • Previously unused 1/2" section removed to prevent precursor mixing

  • Box made of 4 piece 1.6mm thick bent sheet metal

    • Bolted together with M3 screws

  • Manifold supported by ALD valve collar with 3/8"-16 U bolts mounted to box ceiling

  • Single hinge and latch using #6 screws

  • Mounts to 8020 stand with M5 screws

  • Cutouts for:

    • Inlet and outlet for carrier gas and precursors

      • 1/4" steel tubes wrapped with heat tape

    • 3 sets of heat tape and thermocouple

      • 1 for manifold and outlet line

      • 2 for TMIn and TDMSn ampules

    • ALD Valves power and control wires

    • ALD Valve N2 supply

    • Exhaust for KF40 bulkhead flange

    • Vent holes on 2 sides for exhaust airflow

• Submitted safety review of earlier prototype to Matt

• BOM:

Struggles:

• balancing time with school work to get design finished

• we planned to order last Friday but wasn't able to get that ready in time

To do for this week:

• Confirm inlet and outlet configuration

• Make any final adjustments to sheet metal

• Finalize BOM and order everything before Tuesday

  • still need to set up a Send Cut Send Quote

• Work on presentation

Packaging

Progress:

• Informed Icey about the recommended 3 micron AL pad thickness from this article

  • https://lnf-wiki.eecs.umich.edu/wiki/Wire_bonding#Design_considerations

• Also got registered to work in MEMS lab

• Joel and I have been thinking that jumping to chip on PCB packaging will be much eaiser to implement bc we can reduce the complexity and number of process steps in packaging manufacturing

• we should be able to cover up the chip with lower risk of contamination by 3D printing a cap that is much larger than the chip itself and screw mount to through holes on the board

• I don't think this will change anything on EDA's side but ran it by Icey to check

Struggles:

• making enough time for packaging due to time spent on school work and trying to make ALD deadlines

To do this week:

• work on presentation

• should be able to start PCB design once we get the thumbs up from Icey and EDA team

  • need to get footprint of analyzer connector

  • create footprint for wire bond pad pattern

  • consider things like decaps for the board...?

• hoping to mill the board this weekend and be ready for resistor lab chip to be made

Weekly Update #3:

ALD:

• Ordering for sealing unused section:

• Planned out rough cutout locations for delivery storage

• Created rough CAD for delivery storage

  • Have a rough concept for fixturing the manifold by holding onto the unused section

  • 
  • 

• Had a rough week with school work so challenge has been to get good progress on CAD :(

• Planning to get the design to have finalized dimensions and complete for manufacturing this week

  • Need to add concept for holding the bottom of ampules as well

    • will have to think a lot about how tool access will be like given limited space

  • Really hoping to make the Friday ordering deadline for SendCutSend

  • Also need to double check dimensions of hardware and communicate with Viswesh to make sure that routing will be successful

Packaging:

• Worked with Icey and EDA team on plans for first package:

  • Will design and build a 16 pin DIP package for 2 major uses:

    • Wire bond resistance testing

    • MOSFET testing

• Wire bond test:

  • Basically a similar setup to resistor lab, except the N channel conduction path width is being varied in order to keep wire bond pad locations roughly similar

  • Will consist of multiple patterns on the chip for both yield issues and for testing different pad sizes for performance

    • Gave them at least 200um x 200um pads and 300-500um spacing

    • the package for resistance testing will be open top so we can wire bond to different patterns with varying pad sizes by snipping and rebonding after each CV test

  • 

• MOSFET Testing:

  • will have 5 NMOS requireing 15 I/O and 1 GND

  • still in the planning and design stage but can use the same package as resistance testing

• Meeting notes:

  • collaborations between Metrology and EDA group:

    1. (Gina Seo and Sandra You) DRC provides Resistor lab pattern but with pads added on at the peripheral ( pad size > 200umx200um and 300um-500um spacing between pads)

    2. (Gongwei Wang) I/O information (numbers and types of pad for future circuit design, atm: 3 terminal MOSFET 16(5mosx3pads+1gnd) ),

    3. (James Lin) provides some footprints info, and a sketch of pad locations. Research on different IO pad structures.

• Things to do this week:

  • give EDA pad thickness to design for

    • Need to read over this: https://lnf-wiki.eecs.umich.edu/wiki/Wire_bonding#Design_considerations

  • Come up with a lead frame and encapsulation design

• Things I am struggling with:

  • having enough time to focus on this since am behind on ALD

  • Jaci sent me the wrong file so i have to keep waiting to get MEMS lab access 😭

  • also the ebay lead frame got rejected but it should be ok cuz we have to make our own anyways

Weekly Update #2

ALD:

• Confirmed that current heating tape can be used and need programmable AC power supplies after some research

• Ordered 2 stage regulator for N2 tank: https://store.mathesongas.com/3120a-series-dual-stage-high-purity-regulator-brass/

• For CAD:

  • Made a table spaceclaim based on measurements in the lab to help the ALD team plan positioning and pipe routing

    • 
  • Created a rough model of the ALD manifold to reference for mounting ideas

    • 
  • Talked with Viswesh about possible concepts for supporting the ampules

  • Also considering just switching to AL sheet metal that is a bit thicker than what we have to do away with floppiness concerns - don't anticipate a huge increase in cost

• Currently trying to get CAD ready as soon as possible but currently a bit short on time to head down to lab frequently

• Over the next week I will be trying to get models of ampules and ALD valves in CAD so I can begin work on the enclosure and support structures

• Also need to get the heat tapes out and figure out how exactly we will wrap the manifold

Packaging:

• Currently in process of getting MEMS lab access and took a bit of time to know how to use the wire bonder with Joel

• Ordered some sample leadframes and PCB SMD breakout module

  • https://www.ebay.com/itm/256227046773

  • https://www.amazon.com/Custom-Circuit-Solutions-Integrated-Capacitor/dp/B09XLSY9GJ?source=ps-sl-shoppingads-lpcontext&ref_=fplfs&smid=A2I1FZB08726AV&gQT=1&th=1.

• Tentative decision is PCB mill for lead frame and resin 3D printing for encapsulation

• Confirmed that Ideate offers resin 3D printing and curing for students

• Had a meeting with Icey to discuss plans for working with packaging:

  1. @Gina Seo @Sandra You | EDA DRC provides Resistor lab pattern but with pads added on at the peripheral ( pad size > 200umx200um and 300um-500um spacing between pads)

  2. @Gongwei Wang I/O information (numbers and types of pad for future circuit design, atm: 3 terminal MOSFET 16(5mosx3pads+1gnd) ),

  3. @James Lin [ALD] [Packaging] provides some footprints info, and a sketch of pad locations. Research on different IO pad structures.

• Also got info from Jay that we may need packages for 2 terminal devices

• Going forward I will be looking into possible packages to reference for the resistor lab pattern and 5 MOS pattern and start thinking about how best to distribute pad locations

Weekly Update #1

ALD:

• Got my project proposal for precursor delivery system finished and received feedback on it. Will be waiting on revision from my lead later this week.

• Over the upcoming week I will focus on getting the remaining components for delivery system ordered (KF25 tube fitting, 2 stage regulator, heating tape). Hopefully by Tuesday. I will also find time to figure out the physical design space for the ALD system in our lab in so I can make a general space claim in CAD.

• I'm currently trying to figure out uncertainties with requirements for heating tape and what option would be best for our controls team to interface with. I've added some links in the master doc from this preliminary research.

Packaging:

• Got my project proposal for IC packaging finished and received feedback on it. Will be waiting on revision from my lead later this week.

• I will be working with Joel to get familiarity with the wire bonder in the upcoming week. I will also start picking a suitable package for the planned 1cm x 1cm chip size,

• Currently I'm trying to narrow down manufacturing methods for the lead frame and encapsulation

  • Lead frame:

    • TechSpark has confirmed that we cannot use their laser cutter for copper,

    • Joel said that he has seen people using the CNC mill for this, so I will be waiting on details regarding that.

  • Encapsulation:

    • 3D printing seems like an attractive option due to high resolution and low complexity.

    • Joel said that we can set up the resin printer in his office.

    • I also know that IDEATE does resin printing but need to go down there to confirm availability for non IDEATE students.

    • Still a bit concerned about whether 3dp material can withstand soldering, but there might be workarounds like using sockets

Weekly Update #0

ALD:

• I went through the primer and documentation to understand the basics of the project. I selected the delivery system as my main project for the semester. Current struggle is going to be tracking down CAD that was previously done for the project. I plan to read more into the specific design requirements for the delivery system and look through the CAD to understand what models of existing parts I will need to source/create.

Packaging:

• We started with a rough idea to build our own wirebonder, but after the meeting with Icey from the CMOS team, we decided that using the exisiting one in the MEMs lab is sufficient for this semester. So instead I will be working more on a solution to package our silicon chips for this semester. After talking to Joe, we decided to start by purchasing lead frames for testing and we are having trouble finding a complete DIP package that we can buy online.

• Link to DIP lead frame on ebay: https://www.ebay.com/itm/256227046773

• Some notes from Friday's meeting with Icey:

  • pads will be done with thermal evaporator - has AL capacity

  • we should watch out for resistance at connection

  • at MEMs lab pads are 200umx200um (larger is reccomended), need at least 300um-500um ish between each pad

  • our chips are currently 1cmx1cm

  • bond wires can extend to a few cm long

• Going forward I will look into different options for packaging (pads on PCB or attempt to replicate DIP package from industry) I will also start to explore manufacturing methods and some design requirements for our IC package.