IC Packaging
Hacker Fab DIY IC packaging documentation - as of May 21st, 2025.
Last updated
Hacker Fab DIY IC packaging documentation - as of May 21st, 2025.
Last updated
The overall cost of the package itself is $108.10, the total R&D cost of $195.09.
The table below is the BOM packaging, which can be found here:
Hacker Fab currently utilizes the probing station available at CMU for electrical characterization of its ICs, but these machines have proven difficult to both access and operate. Consequently, the team is developing a DIY probing station at a much lower price in hopes of bringing this capability in house. However, as our ICs eventually get more complex and start to increase in IO counts, characterization with a probing station will also require more time and effort.
In anticipation of this challenge, we are also developing a process for packaging our ICs with the EDA team in order to accommodate for the increased IO counts in order to further close the loop on the team’s process steps, and decrease the time to test more complex ICs in the future.
The main purpose of packaging is to protect the IC from the outside world while still making proper electrical connections to other devices. Packages are often standardized into different form factors for different IO counts and applications.
Many packages in industry are designed for protection against environmental factors such as moisture as to prevent damage to the IC. Materials choices are also important especially for high performance ICs that have high heat dissipation. This means that materials used must have compatible coefficients of thermal expansion in order to prevent thermal stress from damaging the package and chip. They must also be designed to reject sufficient heat from the chip in order to prevent thermal runaway.
The varying requirements for different applications have led to many different packaging technologies in the packaging industry that each have trade offs with each other. In recent years, as the semiconductor industry encounters technical and economic limitations to higher performance gains on the ICs, advanced packaging technologies have emerged as a way to continue improving overall device performance while maintaining economic viability.
With all that said, packages being developed at Hacker Fab will have much less technical requirements due to simpler devices on our ICs and our goal of creating easily replicable solutions.
Metric
Requirement
Mechanical strength
Withstand regular handling
Signal integrity
Minimize parasitic resistance between IC and package
Portability
Adaptable to different ICs and ease of package replacement
Integration
Successfully connect to Analog Discovery 3 analyzer
Replicability
Minimize hard to access material and processes
Cost
Minimize cost where possible
Typical semiconductor packaging process goes through the following steps:
Wafer-level probing for known good die (KGD)
Wafer back grinding
Wafer dicing
Die pick & sort
Die attach to package
Wire bonding or flip chip bonding
Package encapsulation
Packaged die test
Final assembly onto printed circuit board (PCB)
(Hacker Fab: Packaging, Robert M. Radway, 2024)
Due to our aim for simplicity and replicability, we will not need all the steps to this process flow, and the packaging method will determine how many process steps are needed for packaging.
Two main candidates were considered for Hacker Fab:
After evaluating the tradeoffs and benefits between the two methods for packaging, we settled on chip on board mainly due to its less complex manufacturing process and better replicability.
The design matrix for this choice is outlined below:
Complexity
Manufacture Time
Chip Protection
Damage Risk
Portability
Total
Chip on Package
0
0
1
0
1
2
Chip on Board
1
1
1
1
1
5
The major concerns regarding manufacturing complexity is mainly due to the lead frame and encapsulation. With a chip on board, the lead frame can be eliminated, reducing the step of machining small patterns on a piece of thin metal. The encapsulation is also made easier by the fact that the PCB board itself can be used as the bottom part of the encapsulation, requiring only a cap to protect the chip.
Working with the EDA team, we first had to decide the IO counts that the prototype package will accommodate. This was ultimately locked down at 16 pins due to its potential for two main tests that we would like to run:
As explained before, wire bonding connects the IC’s IO pads to metal pads on either the PCB or leadframe, but how is this done?
There are two main methods for wire bonding:
We are planning on using wedge bonding for our packaging due to its higher availability on campus and smaller bond footprint allowing for more margin of error during bonding.
The wire material we are planning to use is aluminum for a number of reasons. Since the team has the most experience with aluminum thermal evaporation, using aluminum wire to bond to aluminum pads on the IC will pose the least risks to defects, especially given our uncertainty of potential failure modes on the IC side. Wedge bonding with aluminum also has much higher mechanical reliability than gold and requires lower temperatures, thus further lowering the failure risk.
Based on recommendations from the lab, we have given some IO pad design parameters as well. The aluminum bonding pads are set to be at least 200µm by 200µm and at least 3µm tall, with about 300µm to 500µm spacing between pads. The EDA team has also designed the resistor pattern with multiple sizes of bond pads to determine the size that will yield the most performance for our team.
The package itself is a smaller piece of PCB with the aforementioned 16 IO pins + 4 GND pins in a dual-inline configuration. The IO pads are also dual-inline on either side of the chip footprint.
The encapsulation was planned to be a 3D printed cap secured with bolts to ensure protection of the IC and wire bonds. The bolted connections will allow for easy removal of the cap to inspect for defects and wire bond failure, as well as giving us the option to redo any failed wire bonds. Since we do not expect to use the test chips for extended periods of time or in harsh conditions, moisture protection with hermetic sealing is not considered within scope.
Finally, I exported the board design and designed a 3D printed cap around the chip. The cap uses four M2 screws and nuts for mounting and has 7.5mm of of vertical space for wire bond loop heights.
For the sake of simplicity and cost, we will be using readily available adhesives to perform the chip attach to board step. This should not pose major concerns especially due to the fact that these test packages are not expected to encounter significant thermal loading and since the team is not planning on doing the wafer thinning step, risk of chip cracking is minimal.
The motherboard is a larger PCB that can accommodate two packages by accepting them with female breadboard headers. Has a 30 pin connector to meet the IO needs of the Analog Discovery 3. This approach will allow us to easily swap out packages without having to spend extra time redoing all the connections to the analyzer.
Once the board was finished, the step file was imported into CAD, and 4 M3 screw mounted bumpers were added as well.
Initially the PCBs were planned to be milled in house, but this was later changed to outsourcing for the following reasons:
Better replicability and access for others, PCB mill is not accessible to everyone
Reasonably low cost to outsource PCB manufacturing
More design freedom, not limited to to two layers and can add vias
For Al wire bonding, PCB bonding pads with ENIG (Electroless Nickel Immersion Gold) plating is recommended for high bonding quality
Thus we outsourced board manufacturing to JLC PCB.
The encapsulation was able to be printed in house out of ABS easily.
The remaining components were sourced from Digikey and McMaster-Carr.
Once the PCBs arrived, a combination of solder reflow and hand soldering was used to connect all the components.
Finally, the resistor chip #656 from the EDA team was adhered with double sided tape and wire bonded to the package board. Due to time constraints, the other resistor chip #657 was not wired. The NMOS chip was not fabricated in time.
Due to manufacturing errors, only four resistors on the chip were good for wire bonding for resistance testing.
We found that setting the bonding power to 300 yielded good results. Due to the asymmetry of chip pad placement the two sides don’t have identical wire lengths (~5mm vs ~7mm).
During the wire bonding process, there were multiple issues:
PCB pads are too far away from the chip
Longer bonds are much more difficult to do
PCB pads are also too spaced out compared to the chip pads, leading to longer wires and mismatch in intended pinouts
Bonds should’ve been made before putting in the headers for more rigid fixturing
Lack of rigidity results in loss of ultrasonic energy
Double sided tape is also not ideal for the same reason
Lastly, the encapsulation and hardware are installed, completing the package.
While waiting for the PCBs to arrive, I did a few wire bonding tests with spare chips from the lab to identify likely failure points in the wire bonding process
Conclusions from the test:
Confirmed that thin and small aluminum pads are very susceptible to flaking off the chip
The most likely failure points were at the wedges where bonding occurs, likely due to the sharp geometry creating high stress points
While the original goal was to get IV curves with the Analog Discovery 3, we were not able to do this in time due to needing a specific current-power adapter. As a result we took resistance measurements with a multimeter on the four resistors and used those values for analysis.
For this set of resistors, the chip pads are 400 x 250 x 3 um in dimension, and the n-channel resistors have widths of 75, 150, 225, and 300 um.
Width
Resistance
75 um
1168 Ω
150 um
579 Ω
225 um
408 Ω
300 um
311.5 Ω
Using this data, I was able to plot measured resistance to the reciprocal of channel width to observe a linear relationship. The intercept represents the total parasitic and contact resistances from the wire bonds and chip pads:
Additionally, the pure contact resistance from the bond points and chip pads can be extrapolated by subtracting the parasitic resistance from the Al wires:
The resistance plots are as follows:
From the analysis, the following is concluded:
Total parasitic resistance per connection: 11 Ω
Contact resistance per connection: 10.6755 Ω
Total aluminum wire parasitic resistance: 0.649 Ω
The project has proven successful over the course of the semester. Despite not all the initial project deliverables being met, I was able work towards a successful packaging solution for Hacker Fab and prove its functionality.
Below are actions and improvements for future semesters:
Wire bond chip #657
Obtain IV curves from both resistor chips with the Analog Discovery 3
Package NMOS chips and verify their characteristics with the Analog Discovery 3
Modify Altium footprint to close the gap between chip and PCB pads for easier wire bondin
Additionally, below are potential projects to look into for future semesters:
DIY wafer dicer that allows for more accurate chip sizes
Revisit chip in package through metal plating on resin 3D prints
Flip chip on board packaging with nickel plated aluminum pads and solder reflow
This semester’s progress serves as a first step to packaging for metrology at Hacker Fab, and hopefully as we make progress toward more complex devices packaging can facilitate efficient testing for those devices.
Hacker Fab: Packaging, Robert M. Radway, 2024.
The main use for packages made this semester will be to use the analyzer to perform tests on IC devices, and so all packages will be designed to port to the analyzer.
The machine we are planning to use is the manual wire bonder in the CMU MEMS lab (). This is the wire bonder in the lab that is the easiest to train on, but if more precision is needed we may pivot to other wire bonders in the lab that offer semi automatic operation. Though the use of lab equipment on campus harms the replicability of this project, the team is hoping to use experience gained from our DIY Probe Station to eventually develop a DIY wire bonder at a much lower cost than on the market.
Source:
Chapter A: Wire Bonding, Nanoscale Research Facility, University of Florida, 2021.
Capabilities: ENIG Plating for Aluminum Wedge Wire Bonding, PCB Trace. (figure 11)
CHIP ON BOARD / WIRE BONDING, Würth Elektronik eiSos GmbH & Co. KG.
Analog Discovery 3, Diligent. (figure 2)
The power of packaging, Texas Instruments. (figure 3)
The Mystery Behind The Globs Of Epoxy, HACKADAY. (figure 4)
Fatigue Design Criteria, Encyclopedia of Materials: Science and Technology, R.I. Stephens. (figure 7)
High precision capillary produced with by HIP processing and polishing technology, Orbray. (figure 8)
West Bond Wire Bonder, Carnegie Mellon ECE Department. (figure 9)
