Gongwei Wang
Last updated
Last updated
My name is Gongwei and I will be working on the EDA device modeling this semester
Weekly Update #0
Created GitBook page.
Weekly Update #1
What was accomplished:
Did preliminary research into Skywater SKY130 PDK, OpenLane, SPICE modeling software.
Collected and read documentation on Open-source tools available for EDA and PDKs
SKY130:
SPICE parameter list:
MOSFET modeling:
Roadblocks:
No roadblocks at the moment.
Plans for the week:
Extracting various preliminary MOSFET parameters for SPICE simulation (such as g_m, lambda, Vth) from some I-V, C-V graphs plotted in the previous semester from Icey.
Weekly Update #2
What was accomplished:
Communicated with Wentao for his NMOS and SRAM I-V data from the previous semester.
Plotted and analyzed preliminary MOSFET parameters for Vth.
Confirmed that we need to collect more data due to the limitations of the existing I-V data points.
Wrote up a plan of equations and different methods of extracting Vth, and lambda.
Roadblocks:
No roadblocks at the moment.
Plans for the week:
Collaborate with Ying to: classify accuracy levels for device parameter extraction and attempt extraction on existing chip 613
Collect more data on Chip 613, most likely using the probe station under a larger range of Vds and Vgs
Continue writeup on the parameter extraction doc of equations and different methods of extracting gm, lambda (Vth is ok).
Weekly Update #3
What was accomplished:
Learned during Tuesday's extra training session details on how to use the probe station and parametric analyzer equipment to prepare for later work measuring and extracting parameters from our fabricated NMOS chips.
Added details to parameter extraction document to have plan of analysis for our necessary SPICE Level 1 MOSFET parameters for simulation.
Roadblocks:
A significant unexpected roadblock was that Chip 613 which we had high hopes of using for performing parameter extraction and further testing with higher V_GS values was nowhere to be found in the lab.
Unfortunately, Chip 516 and 588/587 from Wentao last semester are also missing, which is a major setback where we must now take a step back and perform re-fabrication to have a functional chip to work with.
Plans for next week:
Collaborate with Sandra and Gina to finalize the mask I drew for our test chip with 16 I/O pads, make appropriate adjustments to the Length and Width parameters, and settle on a final mask/layout.
Finalize on testing plans and work with Ying and Felicia to decide on some reasonable DRC estimates for the spacing distances between the MOSFETs on the test chip and the minimum gate extension.
Weekly Update 4
What was accomplished:
Roadblocks:
Chip 493 exhibits large deviations from the theoretical MOSFET behaviors of Id-Vds curves expected. This is likely due to manufacturing defects in chip 493, for example, having a significant source/drain resistance (i.e. high resistance between Al pad and source/drain doped region, or insufficient doping at source/drain to reach Ohmic connection)
The threshold voltage derived from Id-Vgs curves varies at different bias voltages, which has multiple possible causes such as S/D resistance, or inconsistent doping.
Plans for next week:
Begin manufacturing of a higher quality NMOS using the test mask that Felicia drew with 2 rows of MOSFETs for further testing and do probe station data extraction instead of using the old Chip 493.
Continue analysis of non-ideal data collected from Chip 493 testing and research potential causes.
Present on current project progress in Demo 1
Weekly Update 5
What was accomplished:
Presented to the class on Thursday our current progress and I demonstrated the testing plan and preliminary test results I gathered from chip 493 using the probe station. I also showed the 16-pad test chip to-scale layout I created for our wire bonding and packaging collab with Metrology. Also, performed further analysis of the unusual data I had collected from Chip 493 to figure out possible reasons for the non-ideal behavior, and presented them (e.g. S/D doping, body effect, Schottky contact) to the class on Demo day for feedback.
Roadblocks:
The main bottleneck for our whole team is having chips to test and obtain data, thus we need masks generated to use in the stepper for fabricating the new test chip. Currently, Gina and Sandra are re-measuring their scale factor mask so that our final MOSFET dimensions (length/width) are accurate for the mask generation.
Plans for next week:
Work on learning and mastering the chip fabrication flow to produce high-quality chips while waiting for the mask generation scale-factor to be resolved. Possibly get hands-on safety training in the lab, for example HF handling procedures.
Weekly Update 6
What was accomplished:
Roadblocks:
None currently
Plans for new week:
~ Mon - Thurs: Work on fabricating the chip, and most likely will need to debug issues with alignment with multiple exposures and stepper frames. Possibly iterate on design based on practical results and create new masks.
~ Fri - Sun: Probe-station testing the fabricated chip to confirm quality of manufacturing and collect data for validation (Id-Vds, Id-Vgs curves).
Weekly Update 7
What work was done:
Completed HF training and started chip fabrication of 4 chips (2 nmos test chips designed by Felicia and 2 i/o pad test chips for my collab with James) and finished HF etching of all 4 chips following the doping step.
Roadblocks:
Spin coater was found to be broken on Friday, and we were eventually able to fix it with a workaround.
The dopant was expired, but a new batch has already been ordered. Went ahead with the barely expired dopant. Slightly concerned about side effects of the expired chemical on our diffusion quality.
Next Steps:
Continue with the fabrication process of the 4 chips, with patterning, etch, deposition. If we don't run into other unexpected roadblocks, will aim to start probe testing and verifying the manufacturing quality, and consider refab with unexpired dopant.
Weekly Update 8
What work was done:
While waiting for the developer from Nanofab, we explored implementing an LVS operating procedure for our HackerFab process and found K-Layout which has native LVS support. To run LVS, we'd need concrete process parameters for our MOSFET devices in order to create the .lib and .lef files for our manufacturing process, similar to technology libraries provided by foundries like TSMC. After further research, I believe the .lef files are especially important since they contain the physical layout and abstract information of standard cells, macros, or other physical components, while .lib files contain the logical and timing characteristics of those cells, crucial for synthesis and static timing analysis.
After developer was available, immediately continued fabrication of our NMOS characterization chip and I/O pad test chip, applying HMDS and photoresist for all 4 chips, and also patterning for the NMOS chip.
For patterning, we exposed the mask below and then developed it, but the NMOSes gate's features were not resolvable, even under the microscope. This is likely due to issues with the autofocus on the new stepper software and camera setup, so when UV exposing the mask it was out of focus and blurred. I think doing manual focus by adjusting the z-axis can a possible workaround to try next.
After develop:
Roadblocks:
Our lab ran out of developer so we could not fabricate until Thursday.
Initially there was an error in the Fabublox process instructions for HDMS bake time which stated a bake time of 20s, but this turned out to not be enough because after lithography and developing the photoresist no change was visible. Then I checked the SOP for patterning and found it listed a 60s bake time for HMDS and that worked.
The autofocus on the stepper seems to be not working well with the new camera and software setup with the image on-screen being blurry after an autofocus run and needing manual z-axis adjustment. But manual focus is challenging, especially in UV mode where the color contrast is very low and the mask pattern is barely visible.
Next steps:
Weekly Update 9
Work done:
Stepper auto-focus is also broken on the UV mode and we later realized it cannot be relied on, and we actually have to do manual focus. Another is the vacuum system on the spin coater being broken and having to manually stick chips on with tape, which is introducing a lot of contamination. The plasma etcher GUI was also unclear with documentation and the meanings of how its various settings and how it represented set plasma time. It was erroneously displaying a set time of 30 seconds as a "1", which led to a serious confusion where we believe 4 would be 4*30 = 120seconds, and this destroyed two of our chips.
Next steps:
Learn from this experience and continue with steps 23+ of the fabrication process. And also begin lithography for the p+ body contacts after fixing the masks for those.
Weekly Update 10
Roadblocks:
Next steps: Test out possible ways to adapt to the new stepper 7% size increase by either shrinking the mask in a photo editor, or calculating and then creating some borders using the stepper GUI.
Continue with the few remaining steps in the fabrication, calculating multi-layer HF-etch times for the B154 and 700B based on their estimated thickness from spincoat RPM and time. Then just N+ doping and Aluminium evaporation, after which we can carry out probe station testing, but likely with the body contact tied to source, since our Probe station only has 3 voltage/current drivers. Week 12 Update Work done: -Caught up on Ying and Felicia's initial work on device modelling python program, and ran various device modelling flows to test out the procedure and accuracy. -Ran simulations in Cadence Virtuoso using some nmos models that industry standard to gather data for information on I_ds - Vds curves at various V_g values.
-Using the SPICE data, further validated our device_model python script for device parameter extractions, while the non-ideal semi-realistic data gives us a better idea of our program.
Roadblocks:
The data gathered from Virtuoso turned out to have strange curves and turns as seen above which is not ideal. This is likely due to some limitations in the modelling accuracy. a Next steps: Further explore KiCad SPICE modelling and the parameters' effects on those simulation results. Continue investigating and developing the extraction procedure and parameters for LEVEL 2 mosfet modelling.
Designed and hand-drafted a mask for our 16 I/O pad chip that we have planned, with 5 MOSFETs and 1 PSUB body connection.
Redrew a new layout for our 16 I/O pad test chip with exact to-scale dimensions for each layer and updated pad component requirements from the Metrology team. (Pads now 300 x 300 um, Stepper frame 1920by1080 pixels)
Probe tested Chip 493 to get data for Id-Vds and Id-Vgs (at many different Vd bias voltages of 1V, 1.5V, 2V, 3V, 4V, 5V, 6V, 7V, 8V) to use in our parameter extraction flow.
Further refined my hand-drawn mask for our 16-pad test chip and finalized on alignment metal patch sizing and width of wires.
Learned how to use Gina and Sandra's mask generation Python tool on Google Colab, and then coded it to generate masks for our 16-pad test chip with metal pads of 300um x 300um and metal_psub contact, to be well-prepared for starting manufacturing.
Adjusted design of 16pad i/o test chip's mask to have greater redundancy for manufacturing process variations, especially in the drc of metal wires. Regenerated all 8 stepper frame masks (with alignment marks) to prepare for next manufacturing step of lithography for the 16 i/o pad test chip. The masks can be found here:
Retry lithography by doing manual focus on the stepper and continue fabrication of the NMOS characterization chip. I believe we can debug the resolution and image focus issues by exposing a resolution test pattern like this:
Doped and HF etched three more chips on Tuesday afternoon and evening, and then on Wednesday, I proceeded to the next steps of patterning with the Mask 1 and Mask 2 of the wire bonding / packaging test chip, and tested out different methods of aligning the two masks vertically and horizontally. Ran into quite a few issues with stepper GUI and the old developer solution, but was eventually able to overcome them. On Thursday, tried to re-expose and develop Mask 3 and Mask 4 onto the packaging test chip, but that accidentally washed away all my previous masks on the chip, and then tried to recoat HMDS and PR to repattern new masks but spin coater vacuum seal was found to be broken. On advice from Discord, went back to lab again to use sticky tape to adhere the chip to the spinner and was able to repattern new masks. However, without the spin coater vacuum, the sticky tape method is much more contamination-prone. During the weekend, went back to lab to continue with next step of our NMOS process with plasma etching and HF etch and Spin-on-glass. Ran into several setbacks with the plasma machine. Initially plasma etch was uneven, and it was likely due to the SF6 pressure regulator which was malfunctioning. Then with another 2 chips, the plasma descum process/sequence's plasma time was set too long which removed too much material and had to be scrapped. Then we learned from this experience and refabricated several new chips, which are now currently at various steps of the process (step 22, step 17, step 12) so that we can continue fabricate and minimize potential setbacks in later steps. Roadblocks: One major issue we experienced was unclear documentation of the stepper GUI, which meant that we were not aware of a rotation setting that was none-zero and was distorting our mask, and the functioning of the many different buttons of "same as pattern" and confusions with whether it automatically converted red to blue for UV exposure.
Work done: Ying, Felicia and I continued fabrication with the knowledge and experience we gained from last week, and this time it went much more smoothly. We were able to do HF etch, then plasma etch (making sure that the SF6 gas output gauge had good pressure ~5 psi), and got clear NMOS characterisation chip patterns done.
Over Spring Carnival, I went ahead and fabricated more steps in the Wire Bonding chip with I/O pads. 700B Non-resist post-bake: PR & Developed P+ body diffusion zone: HF-etched: PR-stripped: Unfortunately the stepper Y-axis calibration was not accurate, and the masks did not overlap, but this will likely not be an issue, as we can have our Metal 1 (Al) deposition bridge the gap anyway on the top layer. I was able to advance the fabrication ahead until the step right ahead of P+ spin-on dopant before discovering a roadblock where the HF etch time is missing in Step 33 of our Fabublox process, which will need to be resolved in our next meeting.
Stepper x-axis micrometer snapped, and the replacement micrometer did not have motor-driven control through the stepper software, so we had to manually control the x-axis movements, which led to overlaps in masks. The spin-coater's vacuum is still broken, forcing us to resort to using double-sided tape. This makes it challenging to remove the chip after a coat and more prone to contamination. Steps 33, 38, 47, and later Wet-etch stages in the Fabublox process are missing Etch Times for all of them, so it was unclear what times I should use. Some experimentation and process development will need to be done. We observed some strange, colorful banding on our chip after plasma etch, which meant we had to scrap it and start over with a new chip. This is perhaps due to insufficient HF etch in the earlier step.
Next steps: Continue quick advancement in the fabrication process now that I am increasingly experienced with the tools and process. During the next meeting, will work with Ying and Icey to figure out the missing HF Etch times for the next steps in Fabublox. Also continue exploring standard cell development and pdk creation. Week 11 Update Work done: We continued fabrication on our pipeline of different chips at various stages of the fabrication process. The packaging chip was completed: Spin-on P+ dopant, Dopant diffusion via tube furnace at 1100 °C for 35 minutes, Spin-on photoresist, and N+ region patterning (where a roadblock was encountered). Currently, our packaging chip is at the furthest stage in the Fabublox process, before we hit a roadblock with the stepper's alignment of overlapping masks, and our NMOS characterization chips have been plasma-etched, HF-etched, survived O2 plasma clean, 700B spun-on & baked for 30 minutes, and are ready for P+ patterning. Post-plasma-O2: Post-non-resist: Roadblocks: The stepper was updated to a new version, and the new version has a resulting pattern size that is approx. 7% larger, so the alignment marks do not exactly line up with the previous exposures I already did on the lower layers (e.g. the poly mask). We also ran into an issue where upon a mode switch the stepper moves it's x and y axis, even though all the checkboxes for autofocus and align stuff are deselected. So when we carefully aligned our n+ mask to overlap with the poly gate in red mode, as soon as switching to UV mode it would throw off the x/y position of the n+ diffusion regions, which made us unable to do the next step of n+ lithography and subsequent doping.
