Felicia Liu
Hi I'm Felicia, I'm working on EDA - Device Modeling :)
Weekly Update #1
Work done:
I drafted project proposal and set goals/timeline on what we plan to achieve this semester with two other teammates in the EDA device modeling subteam (https://docs.google.com/document/d/1sCj4PGeCfQZ3DJODLZkjC7j2guPgpSJxxSDldw_wTm8/edit?tab=t.0).
I focused on figuring out what tool to use for the SPICE model simulation. We decided to go with KiCad's schematic tool which has an embedded open-sourced SPICE simulator Ngspice. It supports custom MOSFET SPICE model definition and can export SPICE netlist from schematics.
Roadblocks:
Had some confusion about which tool was the best to use but resolved.
Plan for next week:
Try simulating with the initial MOSFET model with process parameters calculated from last semester's chip. Figure out what parameter is still needed to build a higher precision MOSFET model and coordinate with other teams involved to develop a testing plan.
Weekly Update #2
Work done:
I worked on writing a dummy MOSFET SPICE model and developing an SOP for SPICE simulation in KiCad (https://docs.google.com/document/d/1_067-FJ9xRFWtv6PRrNWwk6ueBx2oNrUpBuWezrBQxI/edit?tab=t.0). I have figured out how to run DC sweep, plot diagrams, and export SPICE netlist.
Roadblocks:
It is hard to find reliable SPICE documentation. We are having some issues finding the correct way to calculate all the necessary SPICE model parameters from the testing results we currently have. Chips from last semester are not ideal and we are considering fabricating some new chips.
Plan for next week:
Explore more KiCad SPICE functionalities. Research how to calculate parameters, maybe read some textbooks in addition to SPICE documentation.
Weekly Update #3
Work done:
Our group is currently working on developing a test chip for NMOS characterization to collect process parameters and plug them into SPICE model. I worked on designing an initial test chip mask
(https://drive.google.com/file/d/1xJqtZhwv6ymNPnZKm5X7mc3w4kSNG3Up/view).
and helped with coming up with the testing plan (https://docs.google.com/document/d/1wRFp3ccW5n_bPLZD3rvi_6JWFzY__D2YDD_fRpHgOsE/edit?tab=t.0).
I also learned how to use the probe station to test the chip when it comes back.
Roadblocks:
Initially, our group thought we could use the chips from last semester to get the curves needed to calculate the device parameters. However, the working chips were missing so we had to design and refabrication our own chip.
Plan for next week:
The hand-drawn chip masks (one for NMOS characterization by me and one for packaging with I/O pads by Gongwei) need to be finalized with appropriate spacing between components and be transferred to real masks by the mask design group.
Weekly Update #4
Work done:
I kept working on refining the chip mask for device characterization (https://drive.google.com/file/d/1xJqtZhwv6ymNPnZKm5X7mc3w4kSNG3Up/view). Took advice from Icey to add metal pads and detail each layer in color. I referred to the relative ratio of Wentao's working chip mask (https://docs.google.com/presentation/d/14-dpjaqdC6Muq3PNF8Y-pDv0M4lqNexc/edit#slide=id.p2) and came up with DRC width and spacing.
I worked on the presentation slides for our first presentation next week.
Roadblocks:
Currently do not have any roadblocks, just waiting to circle back on the test chip mask design.
Plan for next week:
Finish up the presentation slides and present on Thursday. Collaborate with Gina and Sandra to convert the hand draft test chip design into actual masks. Plug in numbers Gongwei got from chip 493 into SPICE model to verify if the simulation aligns with experimental results.
Weekly Update #5
Work done:
I finished the presentation slides (https://docs.google.com/presentation/d/1tlnXbdm_S4oZerqLOZx2ODcKvoIJ7EftKB4GgxjC8XI/edit) and presented with the group on Thursday. During Q&A, I got feedback on widening contact width for lower contact resistance which is better for NMOS characterization. I made the changes and looked into Sandra and Gina's mask generation codebase to try translating the hand-drawn draft to actual masks (https://colab.research.google.com/drive/1Ihz8MFp59NgdUhTNkJPlqDkgh7zhsC7x?usp=sharing#scrollTo=bWKgX7jIjWGu). Below is the initial result I have. There are a couple of issues:
The codebase does not yet support custom MOSFET length and width.
The exact spacing is unclear.
The scale factor needs to be re-measured (Sandra and Gina working on it).
It is hard to determine the spacing between components on the plotted diagram. Would be helpful if we could work out some sort of reference such as a live ruler tool.
The current design exceeds the area of a single exposure. However, whether or not the final design will exceed depends on the scale factor.
Need to define which layer P+ resides.
Roadblocks:
Waiting for Gina and Sandra to retrieve the accurate scale factor and implement MOSFET W/L customization.
Plan for next week:
Collaborate with Gina and Sandra to solve the above-mentioned issues and work out an initial working mask. Hopefully we can start fabricating soon.
Weekly Update #6
Work done:
I redid the mask design for the NMOS characterization chip. We realized that the scaling on the previous design version was incorrect, and one exposure can fit 5 patterns as shown below without interfering with the focus marks. Metal contact is added onto the MOSFET diffusion. I also collaborated with Sandra to help making the mask generation code more user friendly.
Roadblocks:
Waiting on finalizing the fabrication steps to start fabricating the chip. Also need to finish the HF safety training.
Plan for next week:
Review the mask design with Icey and make any final adjustments. Keep collaborating with Sandra and Gina to think of any other functionalities we should add/brainstorming LVS/DRC design and implementation. Complete HF training and start fabricating test chips.
Weekly Update #7
Work done:
I updated the mask design for the NMOS characterization chip, specifically added Body-Source tie at layout level. This is because the probe station still has only 3 probes and we don't expect an upgrade very soon.
We still plan to fabricate both versions of the chip, with and without BS connection, to ensure flexibility for potential upgrades and the study of body effects. The only difference between the two versions is the metal layer masks as shown below. The rest of the masks can be found in: https://drive.google.com/drive/u/0/folders/1KTrhLrV_Q7-Bw2zknYYuRV_R_0qcSj_h?lfhs=2
We started test chip fabrication. We have 2 NMOS characterization chips and 2 packaging test chips (Gongwei's design). We finished P504 spin-on & diffusion and HF etching (4/4).
Roadblocks:
No roadblocks.
Plan for next week:
Continue to fabricate the chips.
Weekly Update #8
Work done:
This week we discussed next steps we can take other than developing device models. We think we could start looking at open-sourced LVS check tools such as KLayout and brainstorm how they can be integrated with the schematic tool. We also agree that it is too early to develop standard cell library layouts since we are still transferring the layout toolchain and figuring out DRC. However, it is helpful to come up with a list of items we want to build and make constructive suggestions to the process team. Here (https://docs.google.com/document/d/1q6OOcurhvERhzqmwrdqSNwqdjOpPjROsGMo_t2sZ4uE/edit?tab=t.0) I started a documentation.
We continued to fabricate the NMOS characterization chip and the packaging test chip. We spun on HMDS (4/4) and patterned (2/4) our chip. However, the patterning was not successful.
Roadblocks:
The developer was out of stock until Thursday, so we could not fabricate for the first half of the week. The patterning of the two chips was not successful and we think the stepper was not focused properly.
Plan for next week:
Continue to fabricate. Debug the stepper and pattern the two other chips. Do research on KLayout, DRC, and standard cell library options.
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