Gina Seo

Hey! I'm Gina, and I will be working on EDA/PDK this semester.

Update #11

What was accomplished:

• Worked on fabrication of Metrology Resistor chips from Friday-Sunday

  • First chip had issues with etching (as shown on left), so we re-did patterning on it on Sunday and left it in for longer (as shown on right).

After P504 glass on chip#1, chip#2. Overlapping channel region seen above.

chip#1: HF etch time was too short (10s) so did not etch all the way. Redid process below.

chip#1 after patterning and developer again.

chip#2 after patterning and developer

• Completed EDA Bonus credit poster.

Roadblocks: - we were able to get through these roadblocks, but it was mostly about uncertainty of etching time, tool error margins, human mistakes, etc. that delayed our fabrication process. But, we were able to do iterations with feedback from Jay and Icey to figure it out.

Plans for next week:

• Present bonus poster on Thursday!

• Discuss simulation methodology in more specific with Icey to complete before final demos.

Update #10

What was accomplished:

• Created mask instance PCell that creates a psub layer the size of an exposure with alignment crosses in each layer.

• Attempting to develop scripts to export layout views as PNG images, with each "template" instance generating its own specific set of layers.

• Writing out detailed methodology with theory and math for testing minimum trench width.

• Completed Demo Presentation.

Roadblocks: - n/a

Plans for next week:

• Resume metrology chip fabrication.

• Complete basic script for exporting layout views.

• Discuss with Icey the final list of parameters and methodology.

Update #9

What was accomplished:

• Conducted research and drafted a comprehensive write-up on DRC methodology, using PMOS fabrication blocks to identify process limitations and inform rule definitions.
• Edited our MOSFET on KLayout to be accurate orientation; Pictured below is NMOS and PMOS with adjustable parameters (high level and detailed view)

Roadblocks:

• Time conflicts got in the way of syncing about DRC guidelines and methodology in detail with Icey and Sandra over Carnival.

Plans for this week:

• Complete Demo slides and send to Icey for feedback Monday night.

• Figure out exporting masks as files, ideally before demo day.

• Create mask instance for cross alignment marks.

• Create sample DRC script in KLayout.

• Determine detailed methodology with theory + math for some DRC experiments.

Update #8

What was accomplished:

• Created instances in KLayout for resistor and mosfet with adjustable parameters (i.e. segments). Code using Ruby.

  • User can call the instances onto their layout like you would on Cadence.

  

• Uploaded code to github, template can be used to extend with more instances like capacitors, etc.
• Researched general DRC parameters and how the script format is written when inputting into KLayout.

Roadblocks

• Our first attempt after etching with plasma etch wasn't successful; no pattern showed up. So we had to erase and restart.

• When we started to fabricate again, the spinner stopped working due to a malfunction, which stopped us from restarting our fab progress.

  • Instead, we turned to looking at KLayout and spending more time there to create instances and start preparing a user manual for getting around KLayout tools.

Plans for this week:

• Fabricate resistors, if possible.

• If not, develop a mask from KLayout for the resistor and try exporting as GDSII ->convert to png.

• Create a list of parameters (industry-known + Hacker Fab specific) for DRC rules and create action items on how we can start collecting the data for parameters to integrate into DRC scripts as shown below for KLayout.

Update#7

What was accomplished:

• Edited and re-did Fabublox for resistor fabrication after Icey's review
• Completed HF training in class!! (finally)

• Wrote the mid-semester documentation with Sandra, updating our progress on our goals.
• Supported Device Modelling team on debugging code issue for exporting files

• Attempted to fabricate resistors but ran into multiple issues in the fab.

Roadblocks:

• Sandra and I tried to fabricate resistors last Thursday and Sunday but wasn't able to because 1. stepper broke down on Thursday and 2. no developer on Sunday.

  • Delayed with our expected timeline for completing fabrication

Plans for this week:

• Fabrication with Sandra and Icey: Wait for developer to be restocked to do resistor fabrication

  • Take stepper pictures for alignment mark prints for Justin while patterning

• Look forward to HF tutorial/walkthrough on Tuesday to be able to use HF properly and safely

• Explore KLayout and play around with tool's functionality more

• Look through our Fabublox again to make sure each step aligns with SOP standards (i.e. HMDS steps require pre-baking as well)

Update #6

What was accomplished:

• Sandra and I collaborated with Felicia to enhance component generation usability and integrated metal contacts/vias into MOSFET masks.

  
• Remeasured scale factor, and we were slightly off as expected because microscope was not calibrated last time. These are the following measurements:

• Discussed collaboration 2 sub-projects with Stepper team of training new alignment marks on Justin's deep learning algorithm.

  • We are able to modify existing alignment mark detector model with new data instead of creating a new model entirely.

  • Deliverable: EDA team will collect 25-30 images of the new alignment mark under the microscope for sufficient training

  • 2nd Deliverable: Do as many attempts of alignment on stepper by changing angle of stepper to be leveled within tool and shift in x direction only and take note of the number of stepper units it took to get to close alignment. Report to Stepper team.

• Created Fabublox process for the Metrology Resistor test chip; This will be used for next week's fabrication deliverables for Metrology team.

• Downloaded KLayout and followed tutorials on Youtube to learn the shortcuts and tools faster.

  • A particular video that helped a lot was this one on Cell Hierarchy and alignment of masks.

    

    High-level cell view

    

    Can now create many layers

Roadblocks:

• Fabricating chips for Metrology will be slow as Sandra and I need someone to do HF process for us.

Plans for Next Week:

• Do as many attempts of alignment on stepper by changing angle of stepper to be leveled within tool and shift in x direction only and take note of the number of stepper units it took to get to close alignment. Report to Stepper team.

• Collect 25-30 images of the new alignment mark under the microscope for sufficient training

• Continue practicing and creating masks on KLayout during break.

• Begin fabrication for Metrology resistors with Icey and Sandra.

Update #5

What was accomplished:

• Sandra and I completed our demo slides and presented them on Thursday. It went very well as we were able to explain in detail our sub-projects, progress, and justification on decisions we made (i.e. new alignment mark design).

• Sandra and I also prepared a separate demo on Google Colab that included new features of code:

  • Can generate resistor with parametrized number of segments and size of segments

  • Can export all pngs of multi-mask device into each layer for ease

• We started collaborating with the Device Modeling team to help them translate the hand-drawn draft to actual masks using our code base. The new adjustments are made here.

  • Edited our scale in the code so units to um ratio is now 1 to 1 based on our scale factor measurements

  • Added diffusion width and gate size adjustments

  • Finalized dictionary for layers

• Sandra and I selected one tool: KLayout and we determined this by creating a comparison table (also featured in our demo presentation)

  • It will help with future DRC/LVS implementation and is GUI-based.

    

Roadblocks:

• Wasn't able to hold a discussion with stepper team this week on alignment, but will follow up with them on this next week; We also didn't really receive a lot of suggestions for alignment during demo day.

• HF training is not available, so cannot fabricate full devices to test. Will need Icey or another TA who is HF certified to help fab for Metrology resistors in near future.

Plans for Next Week:

• Remeasure scale factor under microscope (was off from last time) and fix in code and definition.

• Fabricate more attempts of resistor pattern on stepper to present to Metrology.

• Download KLayout, create playbook, and experiment with designing a simple mask & exporting files.

• Create plan for moving forward for DRC rule setting

Update #4

What was accomplished:

• Sandra and I patterned again and remeasured the mask design from last week to get the scale factor and graphed with best line of fit.
• Completed the mask design for the resistor lab pattern for the metrology team (code).

  • 
  • Sandra and I fabricated a trial to test alignment between two masks, but the alignment was not very successful. Further trials or a method to precisely locate and overlap previous alignment marks with the next mask's alignment are needed.

  

• Started outlining the demo and preparing slides, aiming to complete them early next week.
• Explored Magic VLSI but found it too outdated; also looked into gdsCAD and KLayout as potential alternatives. Will summarize benefits and tradeoffs of each tool during demo.

Roadblocks:

• Will bring up alignment issues during the demo—currently uncertain about the necessary overlap between masks or whether a patch should be used to connect two diffused areas. Exploring different approaches to solve this issue.

Plans for Next Week:

• Finalize and present demo slides on demo day.

• Incorporate feedback from demo day and collaborate with the Metrology and Stepper team to determine next steps.

• Select one tool from the explored options (gdsCAD, KLayout, etc.) to focus on and deepen understanding.

Update #3

What was accomplished:

1. Patterned chip following the Patterning SOP with mask created from Update #2 on Thursday work session.

   1. Spinner got fixed, so Sandra and I were able to fully work on end-to-end of this mini project. We got to project our mask onto the chip and observe it under the microscope.

   2. However, we were not able to calibrate the microscope to take accurate measurements of sizing because calibration slider wasn't available. Therefore, we've just took measurements using a ruler tool under the 10x microscope as shown below. Given the estimated aspect ratio, we see that it is pretty close.

   
2. Learned functions/scripts for creating layers with phidl & created dictionary framework for organizing diff. layers (multi-layer for metal, poly, oxide, etc.)

   1. Progress of examples is in Colab Notebook in Section "Layers - Learning"
   2. Section "Layers - Organization" contains a structured layer set

   
3. Creates notes on Magic VLSI Tool; Found promising information for possible integration with Hacker Fab processes

Roadblocks

1. Because we couldn't find the calibrating slider to use to get measurements on our masks on the chip, we weren't able to execute our plan of using it to get the scale factor. We will wait until the new order comes in and confirm the scale factor. For now, we will use the scale factor estimation from Kent and the measurements we've taken.

2. I wasn't able to actually walk through the tutorials for Magic VLSI because I don't have a Linux/Windows. A work around may be to run this on ECE computers only, which is fine for the exploration phase.

Plans for Next Week:

1. Sandra and I will focus on working with the Metrology/Packaging team to deliver Resistor lab pattern but with pads added on at the peripheral

2. Look more into Magic VLSI and discuss with Icey to see if this is a promising path to go down.

3. Work with Sandra to talk about how we plan on creating an initial Python framework for NMOS masks that adhere to design guidelines.

Update #2

What was accomplished:

1. Researched design constraints and rules for layout (e.g., spacing, layers). Created notes for future reference.
2. Figured out aspect ratio that reflects Stepper GUI (16:9)

3. Sandra and I recreated the current code as well as the new implementation of critical functions using phidl package tutorial.

4. Sandra and I created masks on Google Colab with rectangles of various sizes to test the scale factor of phidl grid units to micrometers.

1. Went to lab for scale factor on Sunday 1/3, followed SOP for patterning with Kent and learned how to use the stepper.

2. Discussed to the stepper team and Icey, decided to use cross with 1 elongated side as the marker shape of choice for now.

   1. This is because team only cares about rotating 90 degrees.

3. Successfully generated script that turns gds files into a png files.

Roadblocks:

1. Sandra and I were not able to complete patterning to find the scale factor because the spin coater didn't work (the vacuum was too weak so the chip kept falling off during spin).

   1. But, we understood the process of SOP so we believe we can do it once the spin coater is fixed!

Plans for next week:

1. Attempt to pattern a chip with the mask above; take measurements of different rectangles to decide the scale factor.

2. Research Magic VLSI tool.

3. Learn more about the phidl package section: Layers, and how to implement them for more complex masks.

Update #1

What was accomplished:

This week, Icey, Sandra, and I finalized our sub-project for the EDA team to be on mask automation and integrated DRC rules.

a. Sandra and I met on Wednesday, January 22nd to break down our objectives and goals for the project this semester. We established a semester-long plan outlining actionable tasks for each week. We also delved deeper into the background research on mask design and discussed the importance of building DRC rules to better understand the project’s purpose within the scope of HackerFab. We also set up weekly syncs to touch-base on each other's progress.

b. On Thursday, January 23rd, Icey helped refine our project timeline in-class to align with the objectives and deadlines of other teams, ensuring our work can support theirs as well. We planned ahead to allow for buffer time in case we encounter friction with more complicated tasks, which made me feel more comfortable with the final project timeline we decided on.

• Phase 1 (Week 2-6): Allow users to create “instances” of different components with automated mask generation.

• Phase 2 (Week 7-11): Allow instances to have tailorable dimensions and parameters, and start developing a set of DRC rules

• Phase 3 (Week 12-14): Allow users to check masks with DRC rules, and raise warnings when rules are violated.

c. Then, I reviewed the existing codebase and documentation for mask generation in the HackerFab Git repository. I also followed the tutorial to learn the PHIDL package, which the HackerFab Mask Design Program is built on to familiarize myself of what PHIDL can do. I also explored the possibility of building GUIs on PHIDL backends to create a drag-and-drop interface using Tkinter, focusing on how users can dynamically position and parameterize shapes in the layout.

Roadblocks:

a. Sandra and I need to learn how to fabricate single layers to analyze the aspect ratios used in the current mask generation code. Since we haven't started our labs, it holds us back from kickstarting this portion of our project. However, we anticipate learning the required fabrication knowledge starting with Lab 1 this upcoming Thursday.

Plans for next week:

• Continue familiarizing with Python package (PHIDL), current progress, and layer sizing for different devices in the current process. -> Create a Playbook to keep note of important features that will come to use in near future.
• Research design constraints and rules for layout (e.g., spacing, layers) and how to applies to DRC. Look at examples of DRC rules to develop robust checks (especially parameters required).

• Experiment and export GDSII files with Sandra.

• Look forward to resistor fabrication lab to form better idea of how to fabricate single layers on our own.