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Shagun Maheshwari

Weekly Updates for Shagun Maheshwari (CMOS Project)

Update 13;

Progress Update:

Roadblocks:

  • Would be great to get feedback on the N-well 30 sec SOG diffusion chip dopant profile analysis as it looks similar to the 45 second in terms of dopant concentration. Would like to discuss conclusions from this and next steps (for purposes of final documentation, final presentation, and next semesters goals)

Next Steps:

  • Complete Final Presentation slides for CMOS (Due May 2nd)

  • Complete implementing feedback from Final Documentation Rough Draft to create the Final Documentation for submission (Due May 4th)

Feedback

• Cesely Awesome work this semester! Since the 30 sec looks similar to the 45 second I would suggest that we might need to use a lower dopant concentration in our spin on glass. However, as far as I am aware the dopant concentration doesn't get low enough to purchase from Filmtronics. So I would suggest that we might need to look finding ways to redistribute dopant concentration that don't require high temperatures or introduce other impurities into our chips.

Update 12:

Progress tracker: https://github.com/orgs/hacker-fab/projects/34/views/1

Progress Update:

Roadblocks:

  • None as of now

Next steps:

  • Finish fabricating the remaining steps (patterning + Al etching)

  • CV testing

  • Dopant Profile Analysis

  • Poster presentation

  • Final documentation draft

Response:

submitted >24 hrs late.

Good job making fab progress, and thankyou for participating in the showcase!

Update 11:

Progress tracker: https://github.com/orgs/hacker-fab/projects/34/views/1

Progress Update:

Roadblocks:

  • Not having the Aluminium Etchant come in time might be a big roadblock for PMOS (given the fact we are not able to get it from Matt from the nanofab)

Next Steps:

  • Add time details for each step of the PMOS fabublocks process

  • Start fabricating PMOS transistors (Monday, Tuesday, Wednesday, Thursday etc)

  • Start putting together the poster and final documentation

Feedback

• Cesely

Hot Probe Test: Jay and I completed more hot probe tests this weekend. We believe that doping occurs as short as 25s. However, the tests are not the most conclusive. Instead of continuing with PMOS fabrication, we think that it might be better to fabricate more MOSCaps, diodes, and transmission line tests.

MOSCaps: We will be fabricating two types of moscaps: one will be a n-well process MOSCap and the second will be p-substrate MOSCap to use as a reference.

• N-Well MOSCap: For the n-well MOSCap two 30 sec n-well MOSCaps should be fabricated. The reason two needs to be done is that the diffusion time is so short that any small variability can have a large impact on results.

• P-Substrate MOSCap: Another p-substrate MOSCap should be fabricated to compare as a reference. Unlike before, though, there should be a p+ contact fabricated as well. This will be used to compare results. Since Marta’s contacts found that annealing produces more reliable contacts, we would like the p-substrate contacts to be probed both before and annealing to analyze the effects.

Transmission Line: The transmission line test will confirm if our p-channels are achieving an optimal carrier concentration within our fabricated n-wells. The process for this would be to follow or n-well process (short SOG diffusion 30s and 45s and 2-hour drive-in diffusion) followed by doping regions with B-154. In the B154 regions a transmission line can be fabricated. If the contacts are ohmic we have created a p-dope regions with optimal characteristics for p-channels. If the are non-ohmic than we need to increase the carrier concentration. Additionally, given Marta’s findings, you will likely have to anneal the contacts for p-doped region before getting ohmic behavior.

Given the amount of fabrication I would split this between you and Marta. I would expect you to fabricate the two n-well MOSCaps. I would then expect Marta to fabricate and test the p-substrate MOScap and transmission line, since her contacts project primarily used this experimental set up.

We have the chemicals to make our own Al etchant so that should no longer be a roadblock.

Update 10:

Progress tracker: https://github.com/orgs/hacker-fab/projects/34/views/1

Progress Update:

Roadblocks:

  • No actual roadblocks, just haven't been able to fully finish fabrication mainly due to conflicting schedules for when I can be accompanied to lab.

Next Steps:

Fabrication:

  • Fully finish fabrication on Monday

  • Finish CV testing my chip on Monday as well

Analysis:

  • Finish analysis of my, Jay, Cesely, and Marta's chips

Demo presentation:

  • Finish demo 2 presentation

Feedback

• Cesely

Although there were some fabrication challenges this week, the chip completion should have been achievable within the given timeframe. Additionally, my chips are ready for probing, as I mentioned earlier in the week. You're welcome to proceed with probing on your own; having another student present is not necessary. Looking ahead, I hope to see more consistent progress in fabrication, provided there are no major equipment issues.

As far as next steps this week I think our following plan should be:

  • Finalize interpretation of our results.

  • Upon review of our new results, determine finalize our n-well process and move on to fabricating PMOS devices.

  • Based on the new results the model of our doping process should be updated to reflect our experimental results.

Update 9:

Progress tracker: https://github.com/orgs/hacker-fab/projects/34/views/1 Progress Update:

Roadblocks:

  • Scrapping the chips and starting over was a major roadblock that set the project back, however I believe we have a good plan of attack for the next upcoming chips with a detailed process that should prevent errors. Also having seen the issues with wafers, patterning, and developing, it is good experience for the next set of chips. Another learning lesson was realizing that breaking up fabrication over a week causes more issues for the chips. The next set of chips will also have a n+ region in the n-well to prevent Schottky barriers.

Next steps:

Fabrication heavy:

  • Begin fabricating my new set of chips and align on SOG diffusion time with the team.

    • In order to maximize fabrication time at one-go the current plan is to come in majority of the day both Wednesday and Thursday to finish fabrication.

  • Analyze CV data from an fully fabricated chips and run it through my code

Feedback

• Cesely

This weekend Jay and I used a hot probe method to determine when our substrate went from being p-type to n-type to confirm some of our model assumptions. We tested a push through, 15 seconds, 30 seconds, and 1 minute chip and compared this to the bare p-type substrate. We found that the push through, 13s, and 30s did not dope enough to change it to n-type. However, the 1 minute did dope n-type. Due to this, Jay and I believe that we should make chips to test at SOG diffusion times of 30s, 45s, 1 minute, 5 minute, 10 minute, and 30 minutes.

Currently this how we have distributed fabrication roles:

• Jay: 45s and 5 minute

• Ces: 30s and 1 minute

• Shagun: 10 minute

• Marta: 30 minute

Currently, the stepper will not move in the x-direction. As such it will be difficult to fabricate after SOG diffusion (step 11 of the Fabublox). Hopefully this will be fixed before Wednesday so as to not delay fabrication progress.

Unfortunately with fabrication there can be alot of unseen errors that propogate through your process and make our chips unreliable. I would recommend for this next set of chips to make 2 chips both with 10 minute SOG that way we have a back up.

Demo 2 is next week and to start preparing slides. Even if you don't have data yet you can begin outlining your presentation.

Lastly don't forget to update the project tracker.

Update 8:

Progress tracker: https://github.com/orgs/hacker-fab/projects/34/views/1

Progress Update:

  • 85% done fabrication (was in the fab Tuesday, Wed, Thurs, Fri, Sat)

    • Got the second chip up to speed with the first and third (completed etching, RCA, oxide growth, and aluminum evaporation)

    • Fixed the patterning issues with all 3 chips and etching

    • Overcame roadblocks with the stepper and etching

Roadblocks:

  • Had a lot of issues with patterning with the patterns being under developed and over developed. Also an issue with the developer seeming to react with the aluminum. There was also a few issues with the stepper and its updates. As a result I had to pattern and then clean them with acetone & IPA, then re-pattern. The evaporator was also not increasing in pressure so had to pause evaporation.

Next Steps:

  • Finish up fabrication:

    • Evaporation, Patterning, Etching for all 3 chips

  • CV testing the N-well chips

  • Data Analysis on the CV testing results with my parameter extraction code.

  • Put together the Demo 2 presentation

Feedback

• Cesely

It will be imperative that fabrication gets finished at the beginning of this week so that it leaves enough time for data analysis and probing. Marta will be switching to your project which should help expediate fabricating and probing- however, I don’t expect her to fully switch over until after Demo 2. If you let me know this week when you want to be in the lab, I will try to work my schedule to be there.

As far as roadblocks, the evaporator was simply because the gasket for the vent screw came off, which Jay found. The developer may have been etching because the developer not being diluted enough- however, as far as I am aware this was fixed.

When developing you both under and over developed? Did you make note of what times it was under developing and overdeveloping at? I have found that when I fabricate that developing for 1 min. on the dot tends to provide the most consistent and best results.

Update 7:

Progress tracker: https://github.com/orgs/hacker-fab/projects/34/views/1

Progress Update:

Roadblocks:

  • Some major roadblocks occurred this weekend when I went for fabrication due to the stepper borking 2x due to a new software update from the stepper team. Went in to manually change some of the code when it didn't work the second time. As a result my fabrication process on Saturday was halted at the patterning step at 2pm (when I was with Cesely) and then at 6pm (when I was with Jay). Fortunately we resolved the stepper issue at 7pm that Saturday.

  • Once the stepper started working, the developer ran out and based on Jay and I's hypothesis, the little bit of developer left was not diluted and as a result when I tried patterning when the stepper was finally fixed at 7pm on Saturday, the developer reacted with the alumnium and the patterns wouldn't come off with Acetone and IPA. Since the developer ran out we couldn't create new developer and I had to unfortunately put patterning on pause until we get new developer from the nanofab on Monday.

Next Steps:

Fabrication Heavy:

  • Chip 1 & 3:

    • pattern (once the new developer comes), Al etch, HF etch, evaporate, pattern, Al etch, CV test

  • Chip 2:

    • HF etch, RCA clean, oxide growth, evaporation, pattern, Al etch, HF etch, evaporate, pattern, Al etch, CV test

  • CV testing the N-well chips

  • Data Analysis on the CV testing results with my parameter extraction code.

  • Put together the Demo 2 presentation

Feedback

• Cesely This past week a lot of effort was put to fabrication and good progress was made towards it. Unfortunately, with experimental work when equipment is not working or we don’t have the right materials it can seriously stall progress. This week you definitely should prioritize finishing fabrication and extracting results.

Your next steps for this week are spot on. Once we have the data we will be able to determine if we need to continue refining the n-well process or if we can move to incorporating p-channels.

Lastly, last week’s code for CV analysis has some errors in the x-axis. We should not be getting doping depths of thousands of centimeters. When performing analysis this week, please ensure that we are getting realistic results either by correcting the code or analysis process. The reason this may have occurred for the p-substrate is that it is uniform throughout. However, this might not be an issue with the n-well process as it is not doping the entire substrate and will not be uniform.

Update 6:

Progress tracker: https://github.com/orgs/hacker-fab/projects/34/views/1

Progress Update:

  • Conducted an additional CV measurement to gain more datapoints. Noticed that the starting Capacitance values were very different than the measurements we got from CV testing previously (80E-12 vs -5E12). This is a concern and may indicate the need to CV test right after fabrication. Double checked these measurements across different patterns on the chip and got the same results (-5E12) and an unsual pattern. Ensured that the right wires were conducted with Cesely as well. https://drive.google.com/file/d/1xmuh6REhugHDBq0zxFUj4Al5GOF4CdKl/view?usp=drive_link

  • Completed the resistor lab report due this past Thursday https://docs.google.com/document/d/1RwM0FQTVCdrgQPGWhVTY6jXz1YTKiDIETPxuRRbStMo/edit?tab=t.0#heading=h.z0d3bcf842i

  • Wrote a python script to extract doping profile plots from the CV measurements I took (CV analysis code). https://colab.research.google.com/drive/1E--WX9qcv_Ggp_nPVyZ8kAjMGIo1RbDY#scrollTo=Xbv80AJHPoTQ

    • I believe that the initial noise showcased is due to the depletion region not properly being isolated within my script so it is something I will be playing around with / editing.

  • Did a rough calculation with Jay to understand what is our ideal oxide capacitance value based on the variables we have. Noticed it was 20x greater than our first measured oxide capacitance values. Talked to Matt and discussed how it was likely due to contaminants in our oxide due to our fabrication process.

  • Measured the dimensions of the patterns on my p-type moscap to be used in my CV analysis code.

Roadblocks:

  • Unsure about the disparity in CV testing measurements on the same patterns / chips, this will be an area to continuously monitor

  • As it is spring break and last week was midterms, I will get a larger chunk of time to fabricate between the 7th-10th

Next Steps:

  • RCA clean + fabricate the next set of 3 N-well Moscaps. Each N-well Moscap will have a different SOG/Constant source diffusion time to evaluate which is the idea diffusion time for our P504 dopant. This is will occur between March 7th-9th when I get back to Pittsburgh from Spring Break travel.

  • Complete mid-semester documentation by March 9th.

  • Play around further with my Dopant Profile analysis code in order to improve the accuracy of the parameters we are extracting https://colab.research.google.com/drive/1E--WX9qcv_Ggp_nPVyZ8kAjMGIo1RbDY#scrollTo=Xbv80AJHPoTQ

Feedback

• Cesely

Well done this week.

A likely cause of the change in capacitance is just exposure to more contaminants. Based on some quick research humidity (due to condensation or water absorption) and ionic contamination (from body oils, salts, etc.) can reduce the insulation resistance of test fixtures dramatically. This then can alter our measured results.

This week your goal should be to finish fabricating the test chips completely, which you have a good plan for. That way next week you can focus on probing and analyzing results as well putting together presentation #2.

Update 5:

Progress tracker: https://github.com/orgs/hacker-fab/projects/34/views/1

Progress Update:

Roadblocks:

  • Was a bit sick this weekend so wasn't able to complete the full analysis for CV testing

  • Have a midterm heavy upcoming week but will aim to push as much progress

Next Steps:

  • With Cesely's updated code, figure out the constant source diffusion (SOG) diffusion times we will fab on our 3 N-well MOSCAP chips

  • CV testing analysis

  • Resistor Lab report

  • Fabrication

Feedback

• Cesely

Good work this week on the detailed update and the deep dive into CV testing, the demo presentation, and the extensive discussions on the upcoming fab process.

Priorities for This Week:

  • CV Analysis: The analysis was not completed and should be the top priority. Make sure to probe more of the chip to see how much variation there is in our results. While I understand that preparing demos and discussing the fab process can be time-consuming, completing the CV analysis is a critical next step.

  • Fab Process & Fabrication: We need to finalize the fab process for the upcoming chips and start fabrication in the coming weeks. I'm fine with postponing fabrication until next week due to midterms, but it will be our top priority then. If you can begin earlier, that would be an added bonus.

Documentation:

  • The mid-semester documentation is due this week. Document the experiments you have run to date covering theory, fabrication/process, and results.

    • Theory: Describe the type of device you plan to fabricate, the testing methods, and the expected outcomes.

    • Fabrication/Process: Detail how the device is made.

    • Results: Summarize the data collected and provide an interpretation of that data.

You aren’t required to follow this format , but I hope it gives you insight into what we are looking for.

Update 4:

Progress tracker: https://github.com/orgs/hacker-fab/projects/34/views/1

Progress Update:

Roadblocks:

  • Chatted with Cesely and she mentioned it may not make sense to edit the diffusion model code and use that to inform fabing the next set of chips as it is not accurate + a lot of assumptions were made in that model. Her suggestion was to just go ahead with fabing the next set of chips, conduct CV tests, and use those results to inform the parameter changes within the diffusion model. Beleive Jay, Cesely, and I would need to align on this path.

Next Steps:

  • Work on first presentation for Hacker Fab

  • Analyze results from the CV tests

  • Create fabublocks for next set of chips to be fabed

  • Start fabing next set of chips

Feedback

• Cesely Great job on getting your first set of results from a chip! Do you have these results documented, and have you started interpreting them? It's important to begin analyzing your data as soon as possible, as this will be crucial for your presentation and will also help guide the next set of chip fabrications.

Next Steps for CV Testing: One key aspect I want to determine from the CV testing is whether we can back-calculate carrier concentration and junction depth. These parameters will be essential for refining our understanding of the device characteristics.

Future Experiments & Model Refinement: For the next batch of chips, I suggest performing SOG diffusion while varying the drive-in diffusion parameters, specifically time and temperature. The goal is to use these variations to improve the accuracy of the current model. I have concerns about the reliability of my model due to the assumptions and experimental methods used for verification, so updating it with more accurate CV data is a priority.

Action Items: 1. Outline an experimental plan detailing how you will use CV characterization to refine the model. 2. Identify which parameters you will vary and how this will contribute to improving the accuracy of the model. 3. Once the model is updated, we can use it to make informed predictions for optimal doping levels in n-well and CMOS processes.

  • Jay

    • talked with Cesely to clarify, but absolutley use her code from last semester. You need to do this in order to figure out what doping parameters to use when making MOSCaps. The point is to use the model to get close to the desired doping parameters, then test with moscaps, then tune the model, then re iterate on moscap testing with updated model to finalize CMOS doping parameters.

    • use ceselys model to determine what doping parameters you will use for the first set of moscaps, then fab them this week to stay on schedule.

Update 3:

Progress Update:

  • Fabricated a p-type MOScap

    • Completed oxide growth

    • Completed aluminium evaporation

    • Created patterns

    • Patterned

    • Applied photoresist

    • Figured out correct procedure for aluminum etching

    • Learned and used the probe station to see if there was ohmic contact and optimized the aluminum etching process accordingly

    • HF etched the oxide

    • Aluminum evaporated again with new pattern

Roadblocks:

  • Main roadblock was the long time it took to fabricate and improving the aluminum etching process

  • Also had an issue with the evaporator on the second round of aluminum evaporation where the pressure wouldn't drop below 1e-4 hPa

Next Steps:

  • Learn more about CV testing and the procedure we want to follow + understand how to interpret the different results we could see and what that tells us about the device

Responses

• From Cesely

Good work getting a MOSCap fabricated. This week we should perform a CV test on the chip and seeing if we can get the dopant concentration vs. depth and using this to compare with the model I had from last semester. We should also begin fabricating/developing a process to fabricate MOSCaps more akin to the CMOS process we hope to generate.

Also, it is not clear to me which chips you have fabricated. Did you fabricate a chip with or without the RCA clean? Or both? If you only fabricated one chip, then variations in the Al deposition might affect our observed CV results between chips and may not be related to the RCA clean.

Issues with the Al evaporator are likely caused by the chamber not being clean, since it was used this week for labs.

  • From Jay

    • Please make sure to link to the notes/documentation form the fabbing process, ie pics of surface between steps, notes of errors, new findings (like Al etch rate witht eh new ethcant) etc.

    • Make sure task tracker is updated (as per the update rubric)

    • Good job working hard to get a clean moscap fabed and working through difficulties of microfabrication

    • Next steps is a little lacking I would rec

      • perform CV testing on fabed p type moscap

      • Interpret results to attain threshhold voltage, flatband voltage, and dopant profile vs depth.

      • determine doping process for CMOS represntative MOSCaps to be used based on Cesely's code from F24, and make relevant SOPs

      • Begin fabing of CMOS representative MOSCaps (this may be out of scope for the next week)

    • BTW I have the new tubes and push rod for the tube furnace

Update 2:

Progress Update:

Roadblocks:

  • No current roadblocks, tube furnace seemed to have died so couldn't make the p-type MOScap last week but it seems to have been fixed so I can do that next week

Plans:

  • Conduct an RCA clean following my SOP

  • Fab a p-type MOScap

  • Read through chapters 4 and 5 of Modern Semiconductor devices for Integrated circuits again in detail and read through dopant profiles to help with CV testing.

Responses

  • From Cesely

    • Great work this week! Your documentation looks very good and professional.

      It will be imperative that you start fabricating this week as you learned last week things in the lab can take much longer than expected.

      How do you intend to measure the effectiveness of the RCA clean? Will you be comparing the results of the RCA clean by having a baseline chip with no RCA clean?

      Also, will need to make patterns for your MOS Caps. I can review how to do this with you.

  • From Jay

Update 1:

Progress Update:

  • Read through chapters 4 and 5 of Modern Semiconductor devices for Integrated circuits

  • Did research on CV characterization

  • Wrote the Project Proposal for PMOS including Junction Depth and CV characterization

  • Completed pattern training with Jay

Roadblocks:

  • No major roadblocks to report

Plans:

  • Fab a p-type substrate

  • Look more into the specific experiments we should conduct for CV characterization

  • Lab next week

Responses

  • From Jay

    • Critiques: For the progress update, be sure to link to the document(s) that show evidence of your progress. this week that would be a link to you project proposal

      For roadblocks, this is an opportunity to request help, or clarify what you need from us to keep moving forward. I would argue training on certain equipment to be roadblock for you.

      For plans, there should be more detail in how you're going to proceed, or link to your working doc that demonstrates your plans in more detail. For example, Fabing a p type MOSCap will require designing a fabublox process and reviewing it with someone, creating the patterns you're going to use for lithography, etc.

      For CV testing, I understand you will research specific experiments we what to do, but you should include a tentative plan of what readings youre going to look at first. This can help us guide your research more concretely.

      Overall good job!

  • From Cesely

    • Great work this week. I would continue to understand and devise a plant to extract specifically the carrier concentration vs junction depth. Also, this week you should begin to fabricate MOS Caps with a p-type substrate. This will be tentative as we are waiting for a power supply for the Thermal Evaporator. In the meantime you should use Fabublox (link below) to create a fabrication process for the MOS Cap.

Update 0:

Progress Updates

  • Reviewed some documentation from the Project Primer

  • Had initial group meeting with the CMOS team to go over problems

  • Read through assigned readings

Roadblocks

  • No major roadblocks to report

Plans

  • Read through chapter 1,4,5,6 in the Modern Semiconductor Devices for Integrated circuits textbook

  • Read through the documents from the Project Primer

  • Draft project proposal (due Thursday before class)

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