Shagun Maheshwari

Weekly Updates for Shagun Maheshwari (CMOS Project)

Update 8:

Progress tracker: https://github.com/orgs/hacker-fab/projects/34/views/1

Progress Update:

• 85% done fabrication (was in the fab Tuesday, Wed, Thurs, Fri, Sat)

  • Got the second chip up to speed with the first and third (completed etching, RCA, oxide growth, and aluminum evaporation)

  • Fixed the patterning issues with all 3 chips and etching

  • Overcame roadblocks with the stepper and etching

Roadblocks:

• Had a lot of issues with patterning with the patterns being under developed and over developed. Also an issue with the developer seeming to react with the aluminum. There was also a few issues with the stepper and its updates. As a result I had to pattern and then clean them with acetone & IPA, then re-pattern. The evaporator was also not increasing in pressure so had to pause evaporation.

Next Steps:

• Finish up fabrication:

  • Evaporation, Patterning, Etching for all 3 chips

• CV testing the N-well chips

• Data Analysis on the CV testing results with my parameter extraction code.

• Put together the Demo 2 presentation

Feedback

• Cesely

It will be imperative that fabrication gets finished at the beginning of this week so that it leaves enough time for data analysis and probing. Marta will be switching to your project which should help expediate fabricating and probing- however, I don’t expect her to fully switch over until after Demo 2. If you let me know this week when you want to be in the lab, I will try to work my schedule to be there.

As far as roadblocks, the evaporator was simply because the gasket for the vent screw came off, which Jay found. The developer may have been etching because the developer not being diluted enough- however, as far as I am aware this was fixed.

When developing you both under and over developed? Did you make note of what times it was under developing and overdeveloping at? I have found that when I fabricate that developing for 1 min. on the dot tends to provide the most consistent and best results.

Update 7:

Progress tracker: https://github.com/orgs/hacker-fab/projects/34/views/1

Progress Update:

• Completed Mid-semester report https://docs.google.com/document/d/1odQKf4WDqPkViEFZeu7Q-SG1CqEAVUaEjF3_BqbSfB0/edit?usp=sharing

• Edited doping model further https://colab.research.google.com/drive/1bQZgRnmR86xbTDP_NhUrbLdB4IEHjxcc#scrollTo=oWfJk6abFTMl

• Created Fabublocks of the N-well process https://www.fabublox.com/process-editor/482ebf89-52fb-4ae1-a684-64f448e9f30d

• Created the N-well pattern slides https://docs.google.com/presentation/d/1hVJ81RGv6qtCSJhDALb0VnskNpjEpFspkuzATtNKD18/edit?usp=sharing

• 50% done fabrication for the N-well Moscaps (3 chips with varying SOG diffusion times)

  • Chip 1 (5 min SOG diffusion)

    • Finished: SOG diffusion, HF etch, Drive-in diffusion, HF etch, RCA clean, oxide growth, evaporation

  • Chip 2 (10 min SOG diffusion)

    • Finished: SOG diffusion, HF etch, Drive-in diffusion

    • Note: This chip was lost in the fume hood and then found later on, which is why it is at an earlier stage in fabrication than Chip 1 and 3

  • Chip 3 (15 min SOG diffusion)

    • Finished: SOG diffusion, HF etch, Drive-in diffusion, HF etch, RCA clean, oxide growth, evaporation

Roadblocks:

• Some major roadblocks occurred this weekend when I went for fabrication due to the stepper borking 2x due to a new software update from the stepper team. Went in to manually change some of the code when it didn't work the second time. As a result my fabrication process on Saturday was halted at the patterning step at 2pm (when I was with Cesely) and then at 6pm (when I was with Jay). Fortunately we resolved the stepper issue at 7pm that Saturday.

• Once the stepper started working, the developer ran out and based on Jay and I's hypothesis, the little bit of developer left was not diluted and as a result when I tried patterning when the stepper was finally fixed at 7pm on Saturday, the developer reacted with the alumnium and the patterns wouldn't come off with Acetone and IPA. Since the developer ran out we couldn't create new developer and I had to unfortunately put patterning on pause until we get new developer from the nanofab on Monday.

Next Steps:

Fabrication Heavy:

• Chip 1 & 3:

  • pattern (once the new developer comes), Al etch, HF etch, evaporate, pattern, Al etch, CV test

• Chip 2:

  • HF etch, RCA clean, oxide growth, evaporation, pattern, Al etch, HF etch, evaporate, pattern, Al etch, CV test

• CV testing the N-well chips

• Data Analysis on the CV testing results with my parameter extraction code.

• Put together the Demo 2 presentation

Feedback

• Cesely This past week a lot of effort was put to fabrication and good progress was made towards it. Unfortunately, with experimental work when equipment is not working or we don’t have the right materials it can seriously stall progress. This week you definitely should prioritize finishing fabrication and extracting results.

Your next steps for this week are spot on. Once we have the data we will be able to determine if we need to continue refining the n-well process or if we can move to incorporating p-channels.

Lastly, last week’s code for CV analysis has some errors in the x-axis. We should not be getting doping depths of thousands of centimeters. When performing analysis this week, please ensure that we are getting realistic results either by correcting the code or analysis process. The reason this may have occurred for the p-substrate is that it is uniform throughout. However, this might not be an issue with the n-well process as it is not doping the entire substrate and will not be uniform.

Update 6:

Progress tracker: https://github.com/orgs/hacker-fab/projects/34/views/1

Progress Update:

• Conducted an additional CV measurement to gain more datapoints. Noticed that the starting Capacitance values were very different than the measurements we got from CV testing previously (80E-12 vs -5E12). This is a concern and may indicate the need to CV test right after fabrication. Double checked these measurements across different patterns on the chip and got the same results (-5E12) and an unsual pattern. Ensured that the right wires were conducted with Cesely as well. https://drive.google.com/file/d/1xmuh6REhugHDBq0zxFUj4Al5GOF4CdKl/view?usp=drive_link

• Completed the resistor lab report due this past Thursday https://docs.google.com/document/d/1RwM0FQTVCdrgQPGWhVTY6jXz1YTKiDIETPxuRRbStMo/edit?tab=t.0#heading=h.z0d3bcf842i

• Wrote a python script to extract doping profile plots from the CV measurements I took (CV analysis code). https://colab.research.google.com/drive/1E--WX9qcv_Ggp_nPVyZ8kAjMGIo1RbDY#scrollTo=Xbv80AJHPoTQ

  • I believe that the initial noise showcased is due to the depletion region not properly being isolated within my script so it is something I will be playing around with / editing.

• Did a rough calculation with Jay to understand what is our ideal oxide capacitance value based on the variables we have. Noticed it was 20x greater than our first measured oxide capacitance values. Talked to Matt and discussed how it was likely due to contaminants in our oxide due to our fabrication process.

• Measured the dimensions of the patterns on my p-type moscap to be used in my CV analysis code.

Roadblocks:

• Unsure about the disparity in CV testing measurements on the same patterns / chips, this will be an area to continuously monitor

• As it is spring break and last week was midterms, I will get a larger chunk of time to fabricate between the 7th-10th

Next Steps:

• RCA clean + fabricate the next set of 3 N-well Moscaps. Each N-well Moscap will have a different SOG/Constant source diffusion time to evaluate which is the idea diffusion time for our P504 dopant. This is will occur between March 7th-9th when I get back to Pittsburgh from Spring Break travel.

• Complete mid-semester documentation by March 9th.

• Play around further with my Dopant Profile analysis code in order to improve the accuracy of the parameters we are extracting https://colab.research.google.com/drive/1E--WX9qcv_Ggp_nPVyZ8kAjMGIo1RbDY#scrollTo=Xbv80AJHPoTQ

Feedback

• Cesely

Well done this week.

A likely cause of the change in capacitance is just exposure to more contaminants. Based on some quick research humidity (due to condensation or water absorption) and ionic contamination (from body oils, salts, etc.) can reduce the insulation resistance of test fixtures dramatically. This then can alter our measured results.

This week your goal should be to finish fabricating the test chips completely, which you have a good plan for. That way next week you can focus on probing and analyzing results as well putting together presentation #2.

Update 5:

Progress tracker: https://github.com/orgs/hacker-fab/projects/34/views/1

Progress Update:

• Did an in depth deep dive into CV testing and extracting dopant concentration, dopant profile, junction depth from CV measurements. Notes: https://docs.google.com/document/d/1rfdL9Ypr3_JzwIx1Obn2l71P70NSGfTt9WlnXYr3Q34/edit?tab=t.0#heading=h.t1vhkaq9dye0

• Put together the Demo 1 presentation for Hacker Fab and presented it: https://docs.google.com/presentation/d/1sbkR2R6tLvjAYCmGAw-rUHeOSoS4zhoQOcE0l_GfS_Q/edit#slide=id.g3373c10cf4b_0_288

• Finished all testing for the resistor lab and collected pictures

• Did an in depth code walkthrough with Cesely for the Diffusion Model to understand its limitations and capabilities (1.5 hours) https://colab.research.google.com/drive/1_KY15QEsGiW_qM6DI9G2ryNJ_q8Hdyiz#scrollTo=6ivcaIbc3fLF

• Had an in depth discussion on the patterns + experiments for the N-well MOSCAP we will fab next. The goal is to fab 3 chips at the same time with a CV test and transmission line test on each chip. Each chip will have different constant source diffusion times to test. https://docs.google.com/document/d/1UUBJwmIzOASs8iViaeoWSC-DHOq_JzK7mthqLg3Q0M8/edit?tab=t.0

Roadblocks:

• Was a bit sick this weekend so wasn't able to complete the full analysis for CV testing

• Have a midterm heavy upcoming week but will aim to push as much progress

Next Steps:

• With Cesely's updated code, figure out the constant source diffusion (SOG) diffusion times we will fab on our 3 N-well MOSCAP chips

• CV testing analysis

• Resistor Lab report

• Fabrication

Feedback

• Cesely

Good work this week on the detailed update and the deep dive into CV testing, the demo presentation, and the extensive discussions on the upcoming fab process.

Priorities for This Week:

• CV Analysis: The analysis was not completed and should be the top priority. Make sure to probe more of the chip to see how much variation there is in our results. While I understand that preparing demos and discussing the fab process can be time-consuming, completing the CV analysis is a critical next step.

• Fab Process & Fabrication: We need to finalize the fab process for the upcoming chips and start fabrication in the coming weeks. I'm fine with postponing fabrication until next week due to midterms, but it will be our top priority then. If you can begin earlier, that would be an added bonus.

Documentation:

• The mid-semester documentation is due this week. Document the experiments you have run to date covering theory, fabrication/process, and results.

  • Theory: Describe the type of device you plan to fabricate, the testing methods, and the expected outcomes.

  • Fabrication/Process: Detail how the device is made.

  • Results: Summarize the data collected and provide an interpretation of that data.

You aren’t required to follow this format , but I hope it gives you insight into what we are looking for.

Update 4:

Progress tracker: https://github.com/orgs/hacker-fab/projects/34/views/1

Progress Update:

• Successfully used the Keithley 4200 to conduct CV tests for the fabed p-type MOSCap. https://docs.hackerfab.org/home/standard-operating-procedures/probe-station-sop

  • Ran high and low frequency CV tests and compared it to target CV curves for the accumulation, depletion, and inversion regions for a p-type MOSCap. Stored the data for 4 patterns on the chip

  • Debugged the Keithley 4200 controls

  • Read/skimmed through the Keithley 4200 CV test manual https://download.tek.com/document/4200%20CV%20ApplicationsGuide.pdf

  • Watched Sam Zeloof's CV testing video https://www.youtube.com/watch?v=v6Mb7J6c6og

  • Read through these two documents on CV testing Sam Zeloof linked

    • http://sam.zeloof.xyz/wp-content/uploads/2021/01/CV-resource1.pdf

    • http://sam.zeloof.xyz/wp-content/uploads/2021/01/CV-resource2.pdf

• Did a code walkthrough with Cesely for the diffusion model and loaded/ran it in google colab https://colab.research.google.com/drive/1cJ8WHxEa8jF9vQnLNw5twRnWye24PjPx

Roadblocks:

• Chatted with Cesely and she mentioned it may not make sense to edit the diffusion model code and use that to inform fabing the next set of chips as it is not accurate + a lot of assumptions were made in that model. Her suggestion was to just go ahead with fabing the next set of chips, conduct CV tests, and use those results to inform the parameter changes within the diffusion model. Beleive Jay, Cesely, and I would need to align on this path.

Next Steps:

• Work on first presentation for Hacker Fab

• Analyze results from the CV tests

• Create fabublocks for next set of chips to be fabed

• Start fabing next set of chips

Feedback

• Cesely Great job on getting your first set of results from a chip! Do you have these results documented, and have you started interpreting them? It's important to begin analyzing your data as soon as possible, as this will be crucial for your presentation and will also help guide the next set of chip fabrications.

Next Steps for CV Testing: One key aspect I want to determine from the CV testing is whether we can back-calculate carrier concentration and junction depth. These parameters will be essential for refining our understanding of the device characteristics.

Future Experiments & Model Refinement: For the next batch of chips, I suggest performing SOG diffusion while varying the drive-in diffusion parameters, specifically time and temperature. The goal is to use these variations to improve the accuracy of the current model. I have concerns about the reliability of my model due to the assumptions and experimental methods used for verification, so updating it with more accurate CV data is a priority.

Action Items: 1. Outline an experimental plan detailing how you will use CV characterization to refine the model. 2. Identify which parameters you will vary and how this will contribute to improving the accuracy of the model. 3. Once the model is updated, we can use it to make informed predictions for optimal doping levels in n-well and CMOS processes.

• Jay

  • talked with Cesely to clarify, but absolutley use her code from last semester. You need to do this in order to figure out what doping parameters to use when making MOSCaps. The point is to use the model to get close to the desired doping parameters, then test with moscaps, then tune the model, then re iterate on moscap testing with updated model to finalize CMOS doping parameters.

  • use ceselys model to determine what doping parameters you will use for the first set of moscaps, then fab them this week to stay on schedule.

Update 3:

Progress Update:

• Fabricated a p-type MOScap

  • Completed oxide growth

  • Completed aluminium evaporation

  • Created patterns

  • Patterned

  • Applied photoresist

  • Figured out correct procedure for aluminum etching

  • Learned and used the probe station to see if there was ohmic contact and optimized the aluminum etching process accordingly

  • HF etched the oxide

  • Aluminum evaporated again with new pattern

Roadblocks:

• Main roadblock was the long time it took to fabricate and improving the aluminum etching process

• Also had an issue with the evaporator on the second round of aluminum evaporation where the pressure wouldn't drop below 1e-4 hPa

Next Steps:

• Learn more about CV testing and the procedure we want to follow + understand how to interpret the different results we could see and what that tells us about the device

Responses

• From Cesely

Good work getting a MOSCap fabricated. This week we should perform a CV test on the chip and seeing if we can get the dopant concentration vs. depth and using this to compare with the model I had from last semester. We should also begin fabricating/developing a process to fabricate MOSCaps more akin to the CMOS process we hope to generate.

Also, it is not clear to me which chips you have fabricated. Did you fabricate a chip with or without the RCA clean? Or both? If you only fabricated one chip, then variations in the Al deposition might affect our observed CV results between chips and may not be related to the RCA clean.

Issues with the Al evaporator are likely caused by the chamber not being clean, since it was used this week for labs.

• From Jay

  • Please make sure to link to the notes/documentation form the fabbing process, ie pics of surface between steps, notes of errors, new findings (like Al etch rate witht eh new ethcant) etc.

  • Make sure task tracker is updated (as per the update rubric)

  • Good job working hard to get a clean moscap fabed and working through difficulties of microfabrication

  • Next steps is a little lacking I would rec

    • perform CV testing on fabed p type moscap

    • Interpret results to attain threshhold voltage, flatband voltage, and dopant profile vs depth.

    • determine doping process for CMOS represntative MOSCaps to be used based on Cesely's code from F24, and make relevant SOPs

    • Begin fabing of CMOS representative MOSCaps (this may be out of scope for the next week)

  • BTW I have the new tubes and push rod for the tube furnace

Update 2:

Progress Update:

• Did research on performing an RCA clean and wrote the SOP of the RCA clean we will conduct here: https://docs.google.com/document/d/1EJc17dcLvwOp3yGAgUv3rpoIKi2gON022oEVz9VkTkE/edit?usp=sharing

• Added initial notes for RCA clean to the CMOS process dev master doc: https://docs.google.com/document/d/1566Sux3ALGOfexcq4ajqJ6XRDOvNgEnyw1Al20tyuYY/edit?tab=t.0

• Built a FabuBlocks process for the p-type MOScap fabrication here + got feedback from Cesely : https://www.fabublox.com/process-editor/b12fd11e-5a87-4d3f-ad97-d2f436606290

• Created the solutions for SC-1 and SC-2 we will be using for the RCA clean within the fume hood

• Completed phase 1 of the Resistor lab

• Got HF training done

• Got Evaporator training done

• Got Fume Hood training done

Roadblocks:

• No current roadblocks, tube furnace seemed to have died so couldn't make the p-type MOScap last week but it seems to have been fixed so I can do that next week

Plans:

• Conduct an RCA clean following my SOP

• Fab a p-type MOScap

• Read through chapters 4 and 5 of Modern Semiconductor devices for Integrated circuits again in detail and read through dopant profiles to help with CV testing.

Responses

• From Cesely

  • Great work this week! Your documentation looks very good and professional.

    It will be imperative that you start fabricating this week as you learned last week things in the lab can take much longer than expected.

    How do you intend to measure the effectiveness of the RCA clean? Will you be comparing the results of the RCA clean by having a baseline chip with no RCA clean?

    Also, will need to make patterns for your MOS Caps. I can review how to do this with you.

• From Jay

  • Good job getting familiar with the fume hoof and setting up the RCA clean.

  • I gave feedback on fabublox process via discord, but here is what I recommended instead (to ensure we have a surface bulk contact that can be used for testing MOSCaps doped wells too): https://www.fabublox.com/process-editor/4f8374e9-d89c-4486-b54f-716cac33802e

Update 1:

Progress Update:

• Read through chapters 4 and 5 of Modern Semiconductor devices for Integrated circuits

• Did research on CV characterization

• Wrote the Project Proposal for PMOS including Junction Depth and CV characterization

• Completed pattern training with Jay

Roadblocks:

• No major roadblocks to report

Plans:

• Fab a p-type substrate

• Look more into the specific experiments we should conduct for CV characterization

• Lab next week

Responses

• From Jay

  • Critiques: For the progress update, be sure to link to the document(s) that show evidence of your progress. this week that would be a link to you project proposal

    For roadblocks, this is an opportunity to request help, or clarify what you need from us to keep moving forward. I would argue training on certain equipment to be roadblock for you.

    For plans, there should be more detail in how you're going to proceed, or link to your working doc that demonstrates your plans in more detail. For example, Fabing a p type MOSCap will require designing a fabublox process and reviewing it with someone, creating the patterns you're going to use for lithography, etc.

    For CV testing, I understand you will research specific experiments we what to do, but you should include a tentative plan of what readings youre going to look at first. This can help us guide your research more concretely.

    Overall good job!

• From Cesely

  • Great work this week. I would continue to understand and devise a plant to extract specifically the carrier concentration vs junction depth. Also, this week you should begin to fabricate MOS Caps with a p-type substrate. This will be tentative as we are waiting for a power supply for the Thermal Evaporator. In the meantime you should use Fabublox (link below) to create a fabrication process for the MOS Cap.

Update 0:

Progress Updates

• Reviewed some documentation from the Project Primer

• Had initial group meeting with the CMOS team to go over problems

• Read through assigned readings

Roadblocks

• No major roadblocks to report

Plans

• Read through chapter 1,4,5,6 in the Modern Semiconductor Devices for Integrated circuits textbook

• Read through the documents from the Project Primer

• Draft project proposal (due Thursday before class)