Ying Meng
My name is Ying and I will be working on the EDA this semester
Last updated
My name is Ying and I will be working on the EDA this semester
Last updated
I created this Gitbook page.
The EDA team breaks down into Device Modeling and DRC Mask Design. I chose to be in the Device Modeling team helping with creating SPICE model simulation. The three of us wrote the project proposal together here and revised it with Icey. We divided the research work and planned to finish it before our next meeting on Tuesday. I'm in charge of researching MOSFET models with different precision along with the SPICE parameters required from each model and suggest one to follow first. Details of my work are recorded here .
I researched more about SPICE MOSFET level 1. I updated the main documentation with the detailed formulas used to model the level 1 simulation, including current formulas for different MOSFET working regions, explanations and formulas for each SPICE parameter, ways to measure some parameters through experiments, and what limitations this simulation model has.
One roadblock I had was that there is few documentation with enough detailed information for me to fully understand which parameters are necessary for which MOSFET level simulation. I had to research each parameter one by one in detail to see why they are needed and how they are incorporated into the SPICE model. The roadblock is resolved for now, but I'm not sure if I need any help for more precise MOSFET simulation levels.
Next week, I will collaborate with Gongwei to finish developing the parameter extraction method for all parameters for level 1 simulation. I will keep working on level 2 simulation documentation if I have time.
One roadblock our team had was that chip 613, the one with the best experimental result from last semester, disappeared from lab. We were planning on measuring more data with that chip for parameter extraction, but now we have to fabricate a new one, which could delay our progress by a long time.
Next week, we will collaborate with Gina and Sandra to acquire the masks for the chips and start fabricating. I will keep working on level 2 simulation documentation if I have time.
One roadblock for drawing masks is that there are no existing DRC rules for this process. Since we want to derive parameters for device modeling, we want the chip to give consistent curves, so we followed the dimensions from previous successful chips. Another roadblock I encountered is the lack of detailed documentation for SPICE level 2 model.
Next week, we will prepare for the presentation on Thursday. I will mainly present on the SPICE simulation levels and focus on explaining the level 1 model.
Our team did the first demo/presentation on Thursday. I made the slides about SPICE parameters and testing procedures in the shared google slide. I also continued the research on SPICE level 2 model and updated the document with some additional parameters and calculations.
The main roadblock for our team is fabricating the designed chips. We need to coordinate with Gina and Sandra to generate the mask to give to the stepper team. One roadblock I'm having for the level 2 model is the complexity of the calculations. I need to decide whether it is needed to decode all the equations to figure out how to derive the required parameters.
Next week, we can start learning how to fabricate the designed chips while waiting for the mask generation.
The main roadblock now is that I don't know what exact parameters to use for P+ doping processes, such as the heating temperature and time. I need to refer to CMOS process team since they are creating P+ doping process for PMOS.
Next week after sping break, I will add the parameter details for the body diffusion fabrication process referring to PMOS fabrication process. Hopefully they can add a session for HF safety training and we can start fabricating the chip.
Gongwei, Felicia, and I finished HF training and started fabricating our chips. We have 4 chips in total, 2 with packaging and 2 without. We finished doping N+ on the poly layer and etching it out (step 1-5).
One roadblock for developing the process is we do not have previous successful data to back up our thoughts, so we would have to rely on intuition and hope it works.
One roadblock for fabricating is the spin coater broke on the night we went to fabricate, and it was temporarily fixed with a workaround solution.
Next week we will continue to fabricate the chips. We should be able to patten the mosfet gates and finish etching it (step 6-15). If we have more time, we can continue to dope P+ and N+.
While waiting for the developer to be refilled, we discussed the potential of implementing LVS (layout versus schematic) check. We found an open-source tool called klayout, which has built-in LVS check, but we need to provide library files such as .lib, .lef, and qrcTechFile.
Gongwei, Felicia, and I continued fabricating our chips after the developer was refilled. We spinned on HMDS and photoresist for all four chips. We uploaded the chip masks for the MOSFET gates to stepper software and patterned two chips (step 6-11).
One roadblock was the lack of developer until Thursday, so we fabricated only after Thursday.
Another roadblock is the stepper not being able to focus well, especially when it switches to UV mode. So after the chip goes through the developer, we could only see the boundary of the pattern but not the detailed gates.
Next week we will continue to fabricate the chips. We need to figure out why stepper could not focus well and try to find a solution. We should continue patterning the MOSFET gates and finish etching them (step 6-15).
Gongwei, Felicia, and I continued fabricating our chips. We tried manual focus to solve the stepper issue from last week, and were able to pattern two chips successfully with several clear patterns for chip for packaging and for testing. We learned to use the plasma etcher but encountered some problems (explained in the roadblocks section). Most of our chips failed during fabrication, so we made four new ones, which are ready to be patterned.
Roadblocks:
One roadblock was we didn't know what parameters to use for plasma O2 clean. Despite finding the plasma time from the SOP, we were not familiar with the software so we entered the wrong time and caused two patterned chips to be cleaned more than they should be, which led to the pattern disappearing. Another roadblock was the plasma etcher did not etch uniformly for our third chip. I believe our main issue was being not familiar with the fabrication process and tool, and did not have much experience, so we had to do everything several times before succeeding.
Plans for next week:
Next week we will continue to fabricate the new chips. With what we learned from the failed chips, hopefully we should be able to fabricate the gate of the new 4 chips smoothly and start developing source and drain.
Gongwei, Felicia, and I continued fabricating our chips. We HF etched all four new chips and patterned them. This time we learned from previous mistakes and executed each step carefully. We were able to pattern four chips, and two of which displayed very clear results after development. The plasma etching process also went smoothly.
Roadblocks:
One roadblock was that stepper's x-axis motor wasn't working so we had to manually tune the stepper to pattern multiple ones along the x-axis, causing some patterns to overlap.
Another roadblock was that two of the four new chips displayed rainbow-ish colors after development. They went through the exact same process as the two successful chips, so we couldn't figure out what caused the issue.
Plans for next week:
Next week we will continue to fabricate the two successful chips. We will start developing body contact (P+) as the next step. We will also try to design some standard cell masks, such as inverter.
Due to the lack of good synthetic data for device modeling flow, I used Cadence 45nm process and Virtuoso simulator to generate IDS vs. VDS and IDS vs. VGS data. I drew a nmos connected to a 1k ohm resistor schematic, adjusted the nmos length and width to both 10um to match with our process (10um is the largest value it can take), and I also adjusted some other physical parameters such as source-drain width.
I swept VGS and VDS from 0-5V and plotted the current and exported the data into csv file.
Roadblocks:
I found out that cadence 45nm gives results that are very similar to the real chip’s data, but are not close to what we expected as ideal. So we cannot use this data to approach modeling SPICE level 1.
Plans for next week:
We can try to use KiCad with some synthetic SPICE level 1 parameters to generate a graph and plug that graph back into our device modeling flow to fine-tune the script.
We should also think about how to process the more realistic data. Either we process the data so they seem more ideal and plug in model 1, or we research higher-level SPICE models.
Our team learned how to use the probe station to measure I-V curves for MOSFETs. Because of the roadblock described below, we designed two chip masks, one for probe station testing and one for packaged testing, and planned to do parameter extraction based on them after fabrication. I wrote a test plan based on my documentation on MOSFET level 1 SPICE simulation . By measuring ID vs. VGS and ID vs. VDS, we should be able to get the four required parameters for level 1 simulation.
Our team revised the initial draft of two chip masks and the testing plan to better interface with Gina and Sandra's mask generation. I learned the requirements of hand-drawn masks, such as layers, dimensions, DRC rules, etc. I also researched the SPICE level 2 model (Grove-Frohman model) and tried to understand it (reference ).
Icey and I discussed the fabrication process for P+ doping for the NMOS body. We thought of two different methods, using photoresistance or using sacrificial glass, and decided to first proceed with photoresistance because it needs less steps. I then created the new process (link: ), adding steps of body diffusion after step 15 and before source/drain diffusion. I then changed some photoresistance mask patterns for the future steps to adapt the changes.
Cesely, Icey, and I discussed the fabrication process for P+ doping for the NMOS body again, and revised the process (link: ). The process now starts with a 700B glass layer, then etch the pattern for body and dope with P+, next etch the pattern for source and drain and dope with N+. In this way, P+ is diffused twice (1h in total) while N+ is only diffused once (30 min), because the material needs at least 30 minutes to harden and we want the P+ doping to be deeper than the N+ doping.
